Intel's New On-Chip Topology: A Mesh

Since the introduction of the "Nehalem" CPU architecture – and the Xeon 5500 that started almost a decade-long reign for Intel in the datacenter – Intel's engineers have relied upon a low latency, high bandwidth ring to connect their cores with their caches, memory controllers, and I/O controllers.

Intel's most recent adjustment to their ring topology came with the Ivy Bridge-EP (Xeon E5 2600 v2) family of CPUs. The top models were the first with three columns of cores connected by a dual ring bus, which utilized both outer and inner rings. The rings moved data in opposite directions (clockwise/counter-clockwise) in order to minimize latency by allowing data to take the shortest path to the destination. As data is brought onto the ring infrastructure, it must be scheduled so that it does not collide with previous data.

The ring topology had a lot of advantages. It ran very fast, up to 3 GHz.  As result, the L3-cache latency was pretty low: if the core is lucky enough to find the data in its own cache slice, only one extra cycle is needed (on top of the normal L1-L2-L3 latency). Getting a cacheline of another slice can cost up to 12 cycles, with an average cost of 6 cycles. 

However the ring model started show its limits on the high core count versions of the Xeon E5 v3, which had no less than four columns of cores and LLC slices, making scheduling very complicated:  Intel had to segregate the dual ring buses and integrate buffered switches. Keeping cache coherency performant also became more and more complex: some applications gained quite a bit of performance by choosing the right snoop filter mode (or alternatively, lost a lot of performance if they didn't pick the right mode). For example, our OpenFOAM benchmark performance improved by almost 20% by choosing "Home Snoop" mode, while many easy to scale, compute-intensive applications preferred "Cluster On Die" snooping mode.

In other words, placing 22 (E7:24) cores, several PCIe controllers, and several memory controllers was close to the limit what a dual ring could support. In order to support an even larger number of cores than the Xeon v4 family, Intel would have to add a third ring, and ultimately connecting 3 rings with 6 columns of cores each would be overly complex. 

Given that, it shouldn't come as a surprise that Intel's engineers decided to use a different topology for Skylake-SP to connect up to 28 cores with the "uncore." Intel's new solution? A mesh architecture.

Under Intel's new topology, each node – a caching/home agent, a core, and a chunk of LLC – is interconnected via a mesh. Conceptually it is very similar to the mesh found on Xeon Phi, but not quite the same. In the long-run the mesh is far more scalable than Intel's previous ring topology, allowing Intel to connect many more nodes in the future.

How does it compare to the ring architecture? The Ring could run at up to 3 GHz, while the current mesh and L3-cache runs at at between 1.8GHZ and 2.4GHz. On top of that, the mesh inside the top Skylake-SP SKUs has to support more cores, which further increases the latency. Still, according to Intel the average latency to the L3-cache is only 10% higher, and the power usage is lower. 

A core that access an L3-cache slice that is very close (like the ones vertically above each other) gets an additional latency of 1 cycle per hop. An access to a cache slice that is vertically 2 hops away needs 2 cycles, and one that is 2 hops away horizontally needs 3 cycles. A core from the bottom that needs to access a cache slice at the top needs only 4 cycles. Horizontally, you get a latency of 9 cycles at the most. So despite the fact that this Mesh connects 6 extra cores verse Broadwell-EP, it delivers an average latency in the same ballpark (even slightly better) as the former's dual ring architecture with 22 cores (6 cycles average). 

Meanwhile the worst case scenario – getting data from the right top node to the bottom left node – should demand around 13 cycles. And before you get too concerned with that number, keep in mind that it compares very favorably with any off die communication that has to happen between different dies in (AMD's) Multi Chip Module (MCM), with the Skylake-SP's latency being around one-tenth of EPYC's. It is crystal clear that there will be some situations where Intel's server chip scales better than AMD's solution. 

There are other advantages that help Intel's mesh scale: for example, caching and home agents are now distributed, with each core getting one. This reduces snoop traffic and reduces snoop latency. Also, the number of snoop modes is reduced: no longer do you need to choose between home snoop or early snoop. A "cluster-on-die" mode is still supported: it is now called sub-NUMA Cluster or SNC. With SNC you can divide the huge Intel server chips into two NUMA domains to lower the latency of the LLC  (but potentially reduce the hitrate) and limit the snoop broadcasts to one SNC domain.

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  • StargateSg7 - Sunday, August 6, 2017 - link

    Maybe I'm spoiled, but to me a BIG database is something I usually deal with on a daily basis
    such as 500,000 large and small video files ranging from two megabytes to over a PETABYTE
    (1000 Terabytes) per file running on a Windows and Linux network.

    What sort of read and write speeds do we get between disk, main memory and CPU
    and when doing special FX LIVE on such files which can be 960 x 540 pixel youtube-style
    videos up to full blown 120 fps 8192 x 4320 pixel RAW 64 bits per pixel colour RGBA files
    used for editing and video post-production.

    AND I need for the smaller files, total I/O-transaction rates at around
    OVER 500,000 STREAMS of 1-to-1000 64 kilobyte unique packets
    read and written PER SECOND. Basically 500,000 different users
    simultaneously need up to one thousand 64 kilobyte packets per
    second EACH sent to and read from their devices.

    Obviously Disk speed and network comm speed is an issue here, but on
    a low-level hardware basis, how much can these new Intel and AMD chips
    handle INTERNALLY on such massive data requirements?

    I need EXABYTE-level storage management on a chip! Can EITHER
    Xeon or EPyC do this well? Which One is the winner? ... Based upon
    this report it seems multiple 4-way EPyC processors on waterblocked
    blades could be racked on a 100 gigabit (or faster) fibre backbone
    to do 500,000 simultaneous users at a level MUCH CHEAPER than
    me having to goto IBM or HP for a 30+ million dollar HPC solution!
    Reply
  • PixyMisa - Tuesday, July 11, 2017 - link

    It seems like a well-balanced article to me. Sure the DB performance issue is a corner case, but from a technical point of view its worth knowing.

    I'd love to see a test on a larger database (tens of GB) though.
    Reply
  • philehidiot - Wednesday, July 12, 2017 - link

    It seems to me that some people should set up their own server review websites in order that they might find the unbiased balance that they so crave. They might also find a time dilation device that will allow them to perform the multitude of different workload tests they so desire. I believe this article stated quite clearly the time constraints and the limitations imposed by such constraints. This means that the benchmarks were scheduled down to the minute to get as many in as possible and therefore performing different tests based on the results of the previous benchmarks would have put the entire review dataset in jeopardy.

    It might be nice to consider just how much data has been acquired here, how it might have been done and the degree of interpretation. It might also be worth considering, if you can do a better job, setting up shop on your own and competing as obviously the standard would be so much higher.

    Sigh.
    Reply
  • JohanAnandtech - Thursday, July 13, 2017 - link

    Thank you for being reasonable. :-) Many of the benchmarks (Tinymembench, Stream, SPEC) etc. can be repeated, so people can actually check that we are unbiased. Reply
  • Shankar1962 - Monday, July 17, 2017 - link

    Don't go by the labs idiot
    Understand what real world workloads are.....understand what owning an entire rack means ......you started foul language so you deserve the same respect from me......
    Reply
  • roybotnik - Wednesday, July 12, 2017 - link

    EPYC looks extremely good here aside from the database benchmark, which isn't a useful benchmark anyways. Need to see the DB performance with 100GB+ of memory in use. Reply
  • CarlosYus - Friday, July 14, 2017 - link

    A detailed and unbiased article. I'm awaiting for more tests as testing time passes.
    3.2 Ghz is a moderate Turbo for AMD EPYC, I think AMD could push it further with a higher thermal envelope i/o 14 nm process improvement in the coming months.
    Reply
  • mdw9604 - Tuesday, July 11, 2017 - link

    Nice, comprehensive article. Glad to see AMD is competitive once again in the server CPU space. Reply
  • nathanddrews - Tuesday, July 11, 2017 - link

    "Competitive" seems like an understatement, but yes, AMD is certainly bringing it! Reply
  • ddriver - Tuesday, July 11, 2017 - link

    Yeah, offering pretty much double the value is so barely competitive LOL. Reply

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