Memory Subsystem: Bandwidth

Measuring the full bandwidth potential with John McCalpin's Stream bandwidth benchmark is getting increasingly difficult on the latest CPUs, as core and memory channel counts have continued to grow.  We compiled the stream 5.10 source code with the Intel compiler (icc) for linux version 17, or GCC 5.4, both 64-bit. The following compiler switches were used on icc:

icc -fast  -qopenmp  -parallel (-AVX) -DSTREAM_ARRAY_SIZE=800000000 

Notice that we had to increase the array significantly, to a data size of around 6 GB. We compiled one version with AVX and one without. 

The results are expressed in gigabytes per second.

Meanwhile the following compiler switches were used on gcc:

-Ofast -fopenmp -static -DSTREAM_ARRAY_SIZE=800000000

Notice that the DDR4 DRAM in the EPYC system ran at 2400 GT/s (8 channels), while the Intel system ran its DRAM at 2666 GT/s (6 channels). So the dual socket AMD system should theoretically get 307 GB per second (2.4 GT/s* 8 bytes per channel x 8 channels x 2 sockets). The Intel system has access to 256 GB per second (2.66 GT/s* 8 bytes per channel x 6 channels x 2 sockets).

Stream Triad (6 GB)

AMD told me they do not fully trust the results from the binaries compiled with ICC (and who can blame them?). Their own fully customized stream binary achieved 250 GB/s. Intel claims 199 GB/s for an AVX-512 optimized binary (Xeon E5-2699 v4: 128 GB/s with DDR-2400). Those kind of bandwidth numbers are only available to specially tuned AVX HPC binaries. 

Our numbers are much more realistic, and show that given enough threads, the 8 channels of DDR4 give the AMD EPYC server a 25% to 45% bandwidth advantage. This is less relevant in most server applications, but a nice bonus in many sparse matrix HPC applications. 

Maximum bandwidth is one thing, but that bandwidth must be available as soon as possible. To better understand the memory subsystem, we pinned the stream threads to different cores with numactl. 

Pinned Memory Bandwidth (in MB/sec)
Mem
Hierarchy
AMD "Naples"
EPYC 7601
DDR4-2400
Intel "Skylake-SP"
Xeon 8176
DDR4-2666
Intel "Broadwell-EP"
Xeon E5-2699v4
DDR4-2400
1 Thread 27490 12224 18555
2 Threads, same core
same socket
27663 14313 19043
2 Threads, different cores
same socket
29836 24462 37279
2 Threads, different socket 54997 24387 37333
4 threads on the first 4 cores
same socket
29201 47986 53983
8 threads on the first 8 cores
same socket
32703 77884 61450
8 threads on different dies 
(core 0,4,8,12...)
same socket
98747 77880 61504

The new Skylake-SP offers mediocre bandwidth to a single thread: only 12 GB/s is available despite the use of fast DDR-4 2666. The Broadwell-EP delivers 50% more bandwidth with slower DDR4-2400. It is clear that Skylake-SP needs more threads to get the most of its available memory bandwidth.

Meanwhile a single thread on a Naples core can get 27,5 GB/s if necessary. This is very promissing, as this means that a single-threaded phase in an HPC application will get abundant bandwidth and run as fast as possible. But the total bandwidth that one whole quad core CCX can command is only 30 GB/s.

Overall, memory bandwidth on Intel's Skylake-SP Xeon behaves more linearly than on AMD's EPYC. All off the Xeon's cores have access to all the memory channels, so bandwidth more directly increases with the number of threads. 

Testing Notes & Benchmark Configuration Memory Subsystem: Latency
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  • Headley - Friday, July 14, 2017 - link

    I thought the exact same thing Reply
  • JKflipflop98 - Wednesday, July 12, 2017 - link

    For years I thought you were just really committed to playing the "dumb AMD fanbot" schtick for laughs. It's infinitely more funny now that I know you've actually been *serious* this entire time. Reply
  • ddriver - Wednesday, July 12, 2017 - link

    Whatever helps you feel better about yourself ;) I bet it is funny now, that AT have to carefully devise intel biased benches and lie in its reviews in hopes intel at least saves face. BTW I don't have a single amd CPU running ATM. Reply
  • WinterCharm - Thursday, July 13, 2017 - link

    Uh, what are you smoking? this is a pretty even piece. Reply
  • boozed - Tuesday, July 11, 2017 - link

    You haven't done your job properly unless you've annoyed the fanboys (and perhaps even fangirls) for both sides! Reply
  • JohanAnandtech - Wednesday, July 12, 2017 - link

    Wise words. Indeed :-) Reply
  • Ranger1065 - Wednesday, July 12, 2017 - link

    If you are referring to ddriver, I agree, wise words indeed. Reply
  • ddriver - Wednesday, July 12, 2017 - link

    Well, that assumption rests on the presumption that the point of reviews is to upsed fanboys.

    I'd say that a "review done right" would include different workload scenarios, there is nothing wrong with having one that will show the benefits of intel's approach to doing server chips, but that should be properly denoted, and should be just one of several database tests and should be accompanied by gigabytes of databases which is what we use in real world scenarios.
    Reply
  • CoachAub - Wednesday, July 12, 2017 - link

    It was mentioned more than once that this review was rushed to make a deadline and that the suite of benchmarks were not everything they wanted to run and without optimizations or even the usual tweaks an end-user would make to their system. So, keep that in mind as you argue over the tests and different scenarios, etc. Reply
  • ddriver - Thursday, July 13, 2017 - link

    It doesn't take a lot of time to populate a larger database so that you can make a benchmark that involves an actual real world usage scenario. It wasn't the "rushing" that prompted the choice of database size... Reply

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