Sizing Up Servers: Intel's Skylake-SP Xeon versus AMD's EPYC 7000 - The Server CPU Battle of the Decade?
by Johan De Gelas & Ian Cutress on July 11, 2017 12:15 PM EST- Posted in
- CPUs
- AMD
- Intel
- Xeon
- Enterprise
- Skylake
- Zen
- Naples
- Skylake-SP
- EPYC
Intel's New On-Chip Topology: A Mesh
Since the introduction of the "Nehalem" CPU architecture – and the Xeon 5500 that started almost a decade-long reign for Intel in the datacenter – Intel's engineers have relied upon a low latency, high bandwidth ring to connect their cores with their caches, memory controllers, and I/O controllers.
Intel's most recent adjustment to their ring topology came with the Ivy Bridge-EP (Xeon E5 2600 v2) family of CPUs. The top models were the first with three columns of cores connected by a dual ring bus, which utilized both outer and inner rings. The rings moved data in opposite directions (clockwise/counter-clockwise) in order to minimize latency by allowing data to take the shortest path to the destination. As data is brought onto the ring infrastructure, it must be scheduled so that it does not collide with previous data.
The ring topology had a lot of advantages. It ran very fast, up to 3 GHz. As result, the L3-cache latency was pretty low: if the core is lucky enough to find the data in its own cache slice, only one extra cycle is needed (on top of the normal L1-L2-L3 latency). Getting a cacheline of another slice can cost up to 12 cycles, with an average cost of 6 cycles.
However the ring model started show its limits on the high core count versions of the Xeon E5 v3, which had no less than four columns of cores and LLC slices, making scheduling very complicated: Intel had to segregate the dual ring buses and integrate buffered switches. Keeping cache coherency performant also became more and more complex: some applications gained quite a bit of performance by choosing the right snoop filter mode (or alternatively, lost a lot of performance if they didn't pick the right mode). For example, our OpenFOAM benchmark performance improved by almost 20% by choosing "Home Snoop" mode, while many easy to scale, compute-intensive applications preferred "Cluster On Die" snooping mode.
In other words, placing 22 (E7:24) cores, several PCIe controllers, and several memory controllers was close to the limit what a dual ring could support. In order to support an even larger number of cores than the Xeon v4 family, Intel would have to add a third ring, and ultimately connecting 3 rings with 6 columns of cores each would be overly complex.
Given that, it shouldn't come as a surprise that Intel's engineers decided to use a different topology for Skylake-SP to connect up to 28 cores with the "uncore." Intel's new solution? A mesh architecture.
Under Intel's new topology, each node – a caching/home agent, a core, and a chunk of LLC – is interconnected via a mesh. Conceptually it is very similar to the mesh found on Xeon Phi, but not quite the same. In the long-run the mesh is far more scalable than Intel's previous ring topology, allowing Intel to connect many more nodes in the future.
How does it compare to the ring architecture? The Ring could run at up to 3 GHz, while the current mesh and L3-cache runs at at between 1.8GHZ and 2.4GHz. On top of that, the mesh inside the top Skylake-SP SKUs has to support more cores, which further increases the latency. Still, according to Intel the average latency to the L3-cache is only 10% higher, and the power usage is lower.
A core that access an L3-cache slice that is very close (like the ones vertically above each other) gets an additional latency of 1 cycle per hop. An access to a cache slice that is vertically 2 hops away needs 2 cycles, and one that is 2 hops away horizontally needs 3 cycles. A core from the bottom that needs to access a cache slice at the top needs only 4 cycles. Horizontally, you get a latency of 9 cycles at the most. So despite the fact that this Mesh connects 6 extra cores verse Broadwell-EP, it delivers an average latency in the same ballpark (even slightly better) as the former's dual ring architecture with 22 cores (6 cycles average).
Meanwhile the worst case scenario – getting data from the right top node to the bottom left node – should demand around 13 cycles. And before you get too concerned with that number, keep in mind that it compares very favorably with any off die communication that has to happen between different dies in (AMD's) Multi Chip Module (MCM), with the Skylake-SP's latency being around one-tenth of EPYC's. It is crystal clear that there will be some situations where Intel's server chip scales better than AMD's solution.
There are other advantages that help Intel's mesh scale: for example, caching and home agents are now distributed, with each core getting one. This reduces snoop traffic and reduces snoop latency. Also, the number of snoop modes is reduced: no longer do you need to choose between home snoop or early snoop. A "cluster-on-die" mode is still supported: it is now called sub-NUMA Cluster or SNC. With SNC you can divide the huge Intel server chips into two NUMA domains to lower the latency of the LLC (but potentially reduce the hitrate) and limit the snoop broadcasts to one SNC domain.
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tmbm50 - Wednesday, July 12, 2017 - link
Windows licensing is irrespective of virtualization.If you run a vm with a single vCPU on a server with 32 cores, you must license all 32 cores. KVM, ESXi...doesnt matter.
I'm sure most folks ignore that point in the license but if your an enterprise and get audited it's enforced.
nils_ - Wednesday, July 19, 2017 - link
Oracle does the same, and if your environment supports migration to other hosts you'd have to license those too (just in case). It's sort of criminal really.pepoluan - Friday, July 28, 2017 - link
I wonder, though, how does AWS managed to offer per-instance Windows licensing for EC2?Because, by that logic, EVERY Windows instance needs to be licensed against ALL cores in an Availability Zone...
Rοb - Sunday, July 23, 2017 - link
From very brief research it looks like for you're in for $6K per 16 Cores for the Datacenter Edition, trying to run the Software on a 4S 32 Core would cost 64x as much (excluding any Bulk Buy pricing you might be able to request).If you bought SM Fat Twins everything would be separated with less loss of density; for the money saved on Licensing would it pay off.
You want to conduct your business lawfully and can charge the customer what it costs plus profit - that's what it costs, want something different the price will probably be different.
Most Software that has per Core Licenses costs a fair bit and has thought it out so someone can't (lawfully) buy a single License and then run the Software on a much more powerful machine.
Take a deep breath and consider that if you ran it on a Phi x200 in x86 Mode that it would run slowly and you'd be charged for 256 Cores per CPU - so don't do that.
I don't want to sound unsympathetic but if the Vendor didn't make money then they wouldn't have incentive to write the Software.
Convince your customers to switch to free Software or for those prices write your own.
What is the complaint exactly, have a Rack Unit Fee, an Electricity Fee, a CPU Fee, a Software Fee, etc., and tell the customer that XYZ costs that much but if they get WYZ it will only cost so much instead.
Assuming everyone obeys the Law and pays the same for Electricity, Cooling, Electronics, Software and Labor then it's only the percentage of Profit where the difference in price lies - or in other words someone will always charge less (and not be 'audited' / as honest / as intelligent and hard working as your Team).
Let the people who you buy your Software from know your complaint and options, we can't be of much more help to you other than the years of service some of us devote to free and pay Software.
rocky12345 - Wednesday, July 12, 2017 - link
Great article as always I found it very well written and there was a lot of information to take in. It was good to see AMD chips doing this good. Bang for the buck seems to be in AMD's court in both the server market and consumer markets now.To those saying oh in the real world big companies would not be upgrading there software to the latest because of money that may be lost. You guys have a solid point there. BUT these tests are not being done in a real world company that depends on their servers to be up 100% of the time. These are just in house tests done to benchmark the new CPU's so yes the latest and greatest versions of the software can be & should be used. This shows exactly what the new CPU's can do when the software is updated to support the latest and greatest hardware. DO you actually think a huge company when buying new server clusters asks for software that is 5 -10 years olds I am fairly sure they do not. They want the most update to date software that is optimized for the new hardware they are spending big bucks on. They want it to be 100% stable and they also want the latest and greatest because of the fact that they probably will never update the software again or at least not for 5-7 years or more. So testing with old builds of software is very unrealistic and does not show the hardware at it's best and also not what a company is looking fro when buying new hardware.
With that said this is still a great write up and deserves a lot of praise.
rahvin - Wednesday, July 12, 2017 - link
I think it's a great comparison article too, you know it's pretty unbiased when both the Intel and AMD fanboi's are out in force criticizing the article for bias.My main comment is that Intel is crazy with those prices on the platinum chips. Those prices are easily two times the previous generation. This is the result of AMD being absent from the server market, that is Intel running processor prices up to the prices that Sun, IBM and HP used to charge in the worst of the enterprise server days. $13k for a Xeon, you've got to be shitting me.
Here's to hoping AMD mops the floor with them and causes prices to crater just like the last time Opteron was competitive. I remember the days when the highest end Xeon was less than $1000. These days the bottom end Xeons are pricing at $1000 and the high ends are 13X that much. Again, I pray AMD can get 25% market share and knock these prices back into reasonable territory. I also hope AMD makes a ton of money and can keep it up with competitive designs (even if it is doubtful because their management is garbage).
Rοb - Sunday, July 23, 2017 - link
Rahvin writes: "$13K for a Xeon ...".There's more to it than that, read the Fine Print; Intel has all kinds of expensive/inexpensive (depending upon your point of view).
See this Comparison: https://ark.intel.com/compare/120498,120499 .
Which is "less expensive":
Intel® Xeon® Platinum 8180M Processor (28 Cores) for $13,011.00
or
Intel® Xeon® Platinum 8156 Processor (4 Cores) for $7,007.00
So which is less 13 or 7 vs. 28 or 4?
You can't just look at one number.
There are other Technical Points, AMD doesn't have: AVX-512, OmniPath 400Gbps, 8-way Motherboards, etc.
If you MUST have what Intel offers then there's only one choice, if you can work around those things and get along with AMD then you're saving money.
If you wanted bleading edge performance then you'd be looking at Spark or Power; some complain that would deny the ability to play Crysis (and that due to their importance people stay up worrying about their issues).
Which is "best" is often easy to say given a narrow definition, which is best in every possible circumstance can be more of a challenge.
Disclaimer: I don't work at either place and intend to buy Epyc 7nm.
hahmed330 - Wednesday, July 12, 2017 - link
Jolly Good! AMD just smoked Intel's bacon!Impressive showing! Outstanding just outstanding!
Shankar1962 - Wednesday, July 12, 2017 - link
Yeah thats why AMD is still in losses and Intel is making net profits of ~$11billion plus each yearThey are gaining share by trying to sell their so called top products for cheap prices
Wondering who is getting smoked
PixyMisa - Thursday, July 13, 2017 - link
Epyc has been out for three weeks.