Sizing Up Servers: Intel's Skylake-SP Xeon versus AMD's EPYC 7000 - The Server CPU Battle of the Decade?
by Johan De Gelas & Ian Cutress on July 11, 2017 12:15 PM EST- Posted in
- CPUs
- AMD
- Intel
- Xeon
- Enterprise
- Skylake
- Zen
- Naples
- Skylake-SP
- EPYC
SMT Integer Performance With SPEC CPU2006
Next, to test the performance impact of simultaneous multithreading (SMT) on a single core, we test with two threads on the same core. This way we can evaluate how well the core handles SMT.
| Subtest | Application type | Xeon E5-2690 @ 3.8 | Xeon E5-2690 v3 @ 3.5 | Xeon E5-2699 v4 @ 3.6 | EPYC 7601 @3.2 | Xeon 8176 @ 3.8 |
| 400.perlbench | Spam filter | 39.8 | 43.9 | 47.2 | 40.6 | 55.2 |
| 401.bzip2 | Compression | 32.6 | 32.3 | 32.8 | 33.9 | 34.8 |
| 403.gcc | Compiling | 40.7 | 43.8 | 32.5 | 41.6 | 32.1 |
| 429.mcf | Vehicle scheduling | 44.7 | 51.3 | 55.8 | 44.2 | 56.6 |
| 445.gobmk | Game AI | 36.6 | 35.9 | 38.1 | 36.4 | 39.4 |
| 456.hmmer | Protein seq. analyses | 32.5 | 34.1 | 40.9 | 34.9 | 44.3 |
| 458.sjeng | Chess | 36.4 | 36.9 | 39.5 | 36 | 41.9 |
| 462.libquantum | Quantum sim | 75 | 73.4 | 89 | 89.2 | 91.7 |
| 464.h264ref | Video encoding | 52.4 | 58.2 | 58.5 | 56.1 | 75.3 |
| 471.omnetpp | Network sim | 25.4 | 30.4 | 48.5 | 26.6 | 42.1 |
| 473.astar | Pathfinding | 31.4 | 33.6 | 36.6 | 29 | 37.5 |
| 483.xalancbmk | XML processing | 43.7 | 53.7 | 78.2 | 37.8 | 78 |
Now on a percentage basis versus the single-threaded results, so that we can see how much performance we gained from enabling SMT:
| Subtest | Application type | Xeon E5-2699 v4 @ 3.6 | EPYC 7601 @3.2 | Xeon 8176 @ 3.8 |
| 400.perlbench | Spam filter | 109% | 131% | 110% |
| 401.bzip2 | Compression | 137% | 141% | 128% |
| 403.gcc | Compiling | 137% | 119% | 131% |
| 429.mcf | Vehicle scheduling | 125% | 110% | 131% |
| 445.gobmk | Game AI | 125% | 150% | 127% |
| 456.hmmer | Protein seq. analyses | 127% | 125% | 125% |
| 458.sjeng | Chess | 120% | 151% | 125% |
| 462.libquantum | Quantum sim | 91% | 129% | 90% |
| 464.h264ref | Video encoding | 101% | 112% | 112% |
| 471.omnetpp | Network sim | 109% | 116% | 103% |
| 473.astar | Pathfinding | 140% | 149% | 137% |
| 483.xalancbmk | XML processing | 120% | 107% | 116% |
On average, both Xeons pick up about 20% due to SMT (Hyperthreading). The EPYC 7601 improved by even more: it gets a 28% boost on average. There are many possible explanations for this, but two are the most likely. In the situation where AMD's single threaded IPC is very low because it is waiting on the high latency of a further away L3-cache (>8 MB), a second thread makes sure that the CPU resources can be put to better use (like compression, the network sim). Secondly, we saw that AMD core is capable of extracting more memory bandwidth in lightly threaded scenarios. This might help in the benchmarks that stress the DRAM (like video encoding, quantum sim).
Nevertheless, kudos to the AMD engineers. Their first SMT implementation is very well done and offers a tangible throughput increase.
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PixyMisa - Tuesday, July 11, 2017 - link
No, the pricing is correct. The 1P CPUs really are half the price of a single 2P CPU.msroadkill612 - Wednesday, July 12, 2017 - link
Seems to me, the simplest explanation of something complex, is to list what it will not do, which they will not do :(.Can i run a 1p Epyc in a 2p mobo e.g., please?
PixyMisa - Thursday, July 13, 2017 - link
Short answer is no. It might boot, but only half the slots, memory, SATA and so on will be available. Two 1P CPUs won't talk to each other.A 2P Epyc will work in a 1P board though.
cekim - Tuesday, July 11, 2017 - link
One glaring bug/feature of AMD's segmentation relative to Intel's is the utter and obvious crippling of clock speeds for all but the absolute top SKUs. Fewer cores should be able to make use of higher clocks within the same TDP envelope. As a result Intel is objectively offering more and better fits up and down the sweep of cores vs clocks vs price spectrum.So, the bottom line is AMD is saying that you will have to buy the top-end, 4S SKU to get the top GHz for those applications in your mix that won't benefit from 16,18,32,128 cores.
I say all of this as someone who desperately wants EPYC to shake things up and force Intel to remove the sand-bags. I know I'm in a small, but non-zero market of users who can make use of dozens of cores, but still need 8 or fewer cores to perform on par with desktop parts for that purpose.
KAlmquist - Wednesday, July 12, 2017 - link
One possibility is that they have only a small percentage of the chips currently being produced bin well enough to be used in the highest clocking SKU's, so they are saving those chips for the most expensive offerings. Admittedly, that depends on what they are seeing coming off the production line. If they have a fair number of chips where with two very good cores, and two not so good, then it would make sense to offer a high clocking 16 core EPYC using chips with two cores disabled. But if clock speed on most chips is limited due to minor registration errors (which would affect the entire chip), then a chip with only two really good cores would require two localized defects in two separate cores, in addition to very good registration to get the two good cores. The combination might be too rare to justify a separate SKU.I would expect Global Foundries to continue to tweak its process to get better yields. In that case, more processors would end up in the highest bin, and AMD might decide to launch a higher clock speed 16 and 8 core EPYC processors, mostly using chips which bin well enough that they could have been used for the 32 core EPYC 7601.
alpha754293 - Tuesday, July 11, 2017 - link
Why does the Intel Xeon 6142 cost LESS than the 6142M? (e.g. per the table above, 6142 is shown with a price of $5946 while the 6142M costs $2949)ca197 - Tuesday, July 11, 2017 - link
I assume that is the wrong way round on the list. I have seen it reported the other way round on other sites.Ian Cutress - Tuesday, July 11, 2017 - link
You're correct. I've updated the piece, was a misread error from Intel's tables.coder543 - Tuesday, July 11, 2017 - link
On page 6, it says that Epyc only has 64 PCIe lanes (available), but that's not correct. There are 128 PCIe lanes per chip. In a 1P configuration, that's 128 PCIe lanes available. On a 2P configuration, 64 PCIe lanes from each chip are used to connect to the other chip, leaving 64 + 64 = 128 PCIe lanes still available.This is a significant advantage.
Ian Cutress - Tuesday, July 11, 2017 - link
You misread that table. It's quoting per-CPU when in a 2P configuration.