Not Everyone Needs Leading Edge: TSMC’s 22 nm ULP, 12 nm FFC and 12 nm FFC+

Now let’s discuss something less advanced, but what is required for hundreds of millions of devices sold every year.

Advertised PPA Improvements of TSMC's Low-Power/Compact Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  CLN28HPC
vs
CLN28HPM
CLN28HPC+
vs
CLN28HPM
CLN22LPU
vs
CLNHPC+
CLN16FFC
vs
CLN16FF
CLN12FFC
vs
CLN16FFC
12FFC-ULP
vs
CLN12FFC
Power 20% 30% 35% lower 25% lower
Performance - 15% 15% unknown 10% unknown
Area Reduction 10% 10% 10% optional 20% unknown
HVM Start started started 2018 Q1 2016 2018 2019
Note Planar
28 nm-based
FinFET
16/20 nm-based

Development of FinFET-based chips is more expensive of ICs featuring planar transistors and their manufacturing is more costly as well. As a result, FinFET is virtually unavailable for many smaller designers of SoCs that usually build various solutions for emerging IoT applications. GlobalFoundries and Samsung offer their FD-SOI manufacturing processes to such companies (and these technologies have a number of other advantages in addition to being more cost-effective), whereas TSMC intends to introduce its new 22 nm ULP technology aimed at such applications. The CLN22ULP is an optimized version of the company’s 28 nm HPC+ (high-performance compact plus) manufacturing process that has been available for a while. The 22ULP offers a 10% area reduction and either a 15% performance improvement over the 28HPC+ process, or a 35% power drop. The 22ULP process joins a family of other ultra-low-power processes offered by TSMC and will compete against GlobalFoundries 22FDX as well as Samsung’s 28 nm FD-SOI offering.

Next up is TSMC’s 12 nm FFC manufacturing technology, which is an optimized version of the company’s CLN16FFC that is set to use 6T libraries (as opposed to 7.5T and 9T libraries) providing a 20% area reduction. Despite noticeably higher transistor density, the CLN12FFC is expected to also offer a 10% frequency improvement at the same power and complexity or a 25% power reduction at the same clock rate and complexity. Further down the road, TSMC also plans to offer a ULP version of the CLN12FFC with reduced voltage, but that is going to happen only in 2018 or 2019.

Sources: Samsung, TSMC, SemiWiki (123).

Related Reading:

Beyond 10 nm at Samsung: 8 nm and 6 nm
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  • Azethoth - Friday, May 5, 2017 - link

    This is exciting news. The existence of GigaFabs means we must be getting close to the first MegaFab!
  • ishould - Friday, May 5, 2017 - link

    You mean TeraFab?
  • LuckyWhale - Tuesday, May 9, 2017 - link

    I wish Anton would work more on his writing or get a better editor. He writes English so mechanically and itis painfully obvious English is nowhere near his first tongue. I used to follow him at Xbitlabs. Great content but poor writing! sorry.
  • ABR - Thursday, May 11, 2017 - link

    Hmm, normally I'm a stickler about this stuff but with Anton's articles I guess I'm usually so immersed in the content that I don't notice anything!
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  • darkich - Wednesday, May 10, 2017 - link

    Soo..no 7nm on Intel's roadmap?
    Seems like Samsung, GF and TSMC are on their way to leave it in the dust
  • peevee - Friday, May 12, 2017 - link

    The "nodes" are just pure lies at this point. 45nm doubled gate density of 65nm, as expected. 10nm chips should have 20 times more transistors per area unit compared to 45nm. They are not even close. And there is nothing which is really 10nm, even a feature as simple as metal pitch is 40-50nm.
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