Not Everyone Needs Leading Edge: TSMC’s 22 nm ULP, 12 nm FFC and 12 nm FFC+

Now let’s discuss something less advanced, but what is required for hundreds of millions of devices sold every year.

Advertised PPA Improvements of TSMC's Low-Power/Compact Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  CLN28HPC
vs
CLN28HPM
CLN28HPC+
vs
CLN28HPM
CLN22LPU
vs
CLNHPC+
CLN16FFC
vs
CLN16FF
CLN12FFC
vs
CLN16FFC
12FFC-ULP
vs
CLN12FFC
Power 20% 30% 35% lower 25% lower
Performance - 15% 15% unknown 10% unknown
Area Reduction 10% 10% 10% optional 20% unknown
HVM Start started started 2018 Q1 2016 2018 2019
Note Planar
28 nm-based
FinFET
16/20 nm-based

Development of FinFET-based chips is more expensive of ICs featuring planar transistors and their manufacturing is more costly as well. As a result, FinFET is virtually unavailable for many smaller designers of SoCs that usually build various solutions for emerging IoT applications. GlobalFoundries and Samsung offer their FD-SOI manufacturing processes to such companies (and these technologies have a number of other advantages in addition to being more cost-effective), whereas TSMC intends to introduce its new 22 nm ULP technology aimed at such applications. The CLN22ULP is an optimized version of the company’s 28 nm HPC+ (high-performance compact plus) manufacturing process that has been available for a while. The 22ULP offers a 10% area reduction and either a 15% performance improvement over the 28HPC+ process, or a 35% power drop. The 22ULP process joins a family of other ultra-low-power processes offered by TSMC and will compete against GlobalFoundries 22FDX as well as Samsung’s 28 nm FD-SOI offering.

Next up is TSMC’s 12 nm FFC manufacturing technology, which is an optimized version of the company’s CLN16FFC that is set to use 6T libraries (as opposed to 7.5T and 9T libraries) providing a 20% area reduction. Despite noticeably higher transistor density, the CLN12FFC is expected to also offer a 10% frequency improvement at the same power and complexity or a 25% power reduction at the same clock rate and complexity. Further down the road, TSMC also plans to offer a ULP version of the CLN12FFC with reduced voltage, but that is going to happen only in 2018 or 2019.

Sources: Samsung, TSMC, SemiWiki (123).

Related Reading:

Beyond 10 nm at Samsung: 8 nm and 6 nm
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  • Meteor2 - Sunday, May 7, 2017 - link

    Do you mean Broadwell? But what's OC'd clock speed got to do with anything? Reply
  • jjj - Friday, May 5, 2017 - link

    Pretty sure that the 10nm LPE perf claims are vs 14LPE not LPP as 27% higher perf is way too much. Reply
  • Anton Shilov - Friday, May 5, 2017 - link

    Regarding the 10LPE vs 14LP*, I am not sure because we have two statements that contradict each other from Samsung.

    They stated the following in October:

    "Samsung’s new 10nm FinFET process (10LPE) adopts an advanced 3D transistor structure with additional enhancements in both process technology and design enablement compared to its 14nm predecessor, allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption."

    http://www.anandtech.com/show/10765/samsung-10nm-m...

    But if you look at the picture (from August) there (http://images.anandtech.com/doci/10765/dac.png), they mentioned ~30% performance increase at the same leakage power, which can considered as 27%... But if you happen to see some more up to date slides from Samsung, please let me know.
    Reply
  • jjj - Saturday, May 6, 2017 - link

    If they had anywhere close to 27% over 14LPP , they would have more design wins so it's safer to assume that "predecessor" means LPE. The phrasing itself is iffy, why "compared to ïts 14nm predecessor" and not just "compared to 14nm" - corporations are tricky like that. Reply
  • jjj - Sunday, May 7, 2017 - link

    Hong Hao, senior vice president of the foundry business at Samsung Semiconductor "10nm brings a lot of benefits to our customers in terms of area scaling, performance and power or PPA. So overall, the PPA improvements are very substantial compared 14nm. We have compared that in terms of the performance, area and power to 14nm LPE. 14nm LPE is our first-generation finFET technology. We see up to a 30% area reduction with a 27% performance improvement or 40% lower power at the same performance."
    http://semiengineering.com/to-10nm-and-beyond/
    Reply
  • willis936 - Friday, May 5, 2017 - link

    Feynman is crying tears of joy in his grave. Intel is crying for another reason. Reply
  • melgross - Friday, May 5, 2017 - link

    Oh, I don't know. It's acknowledged that Intel's current 14nm process is equivelant to other's 10nm processes, and likely their 10nm will be equivelant to other's 7nm.

    I don't think Intel has anything to,worry about for the next few years. I still doubt that 5nm will come about, at least, not as a real 5nm process, though it will likely be advertised as such.

    But when that wall is reached, for everyone, then, long last, Intel will lose most of its process advantages. But that will be in 5 to 8 years, so there's still a long way to,go.
    Reply
  • tarqsharq - Friday, May 5, 2017 - link

    We'll have to see if we get another materials switch up off silicon.

    Some kind of graphene, maybe a photon based solution instead of electron?

    Apparently quantum computing is only useful for certain types of operations, so that's not a magic bullet for speeding up all of our computing tasks.
    Reply
  • Meteor2 - Friday, May 5, 2017 - link

    I reckon we'll get real 5 nm, probably with quad patterning, possibly with a new transistor design, in around 2023-25. Difficult to see where we can go after that. Maybe that graphene stuff I suppose. Reply
  • vladx - Friday, May 5, 2017 - link

    Nanotubes seems the most feasible solution. Reply

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