Core: It’s all in the Prefetch

In a simple CPU design, instructions are decoded in the core and data is fetched from the caches. In a perfect world, such as the Mill architecture, the data and instructions are ready to go in the lowest level cache at all times. This allows for the lowest latency and removes a potential bottleneck. Real life is not that rosy, and it all comes down to how the core can predict what data it needs and has enough time to drag it down to the lowest level of cache it can before it is needed. Ideally it needs to predict the correct data, and not interfere with memory sensitive programs. This is Prefetch.

The Core microarchitecture added multiple prefetchers in the design, as well as improving the prefetch algorithms, to something not seen before on a consumer core. For each core there are two data and one instruction prefetchers, plus another couple for the L2 cache. That’s a total of eight for a dual core CPU, with instructions not to interfere with ‘on-demand’ bandwidth from running software.

One other element to the prefetch is tag lookup for cache indexing. Data prefetchers do this, as well as running software, so in order to avoid a higher latency for the running program, the data prefetch uses the store port to do this. As a general rule (at least at the time), loads happen twice as often as stores, meaning that the store port is generally more ‘free’ to be used for tag lookup by the prefetchers. Stores aren’t critical for most performance metrics, unless the system can’t process stores quickly enough that it backs up the pipeline, but in most cases the rest of the core will be doing things regardless. The cache/memory sub-system is in control for committing the store through the caches, so as long as this happens eventually the process works out.

Core: More Cache Please

Without having access to a low latency data and instruction store, having a fast core is almost worthless. The most expensive SRAMs sit closest to the execution ports, but are also the smallest due to physical design limitations. As a result, we get a nested cache system where the data you need should be in the lowest level possible, and accesses to higher levels of cache are slightly further away. Any time spent waiting for data to complete a CPU instruction is time lost without an appropriate way of dealing with this, so large fast caches are ideal. The Core design, over the previous Netburst family but also over AMD’s K8 ‘Hammer’ microarchitecture, tried to swat a fly with a Buick.

Core gave a 4 MB Level 2 cache between two cores, with a 12-14 cycle access time. This allows each core to use more than 2MB of L2 if needed, something Presler did not allow. Each core also has a 3-cycle 32KB instruction + 32KB data cache, compared to the super small Netburst, and also supports 256 entries in the L1 data TLB, compared to 8. Both the L1 and L2 are accessible by a 256-bit interface, giving good bandwidth to the core.

Note that AMD’s K8 still has a few advantages over Core. The 2-way 64KB L1 caches on AMD’s K8 have a slightly better hit rate to the 8-way 32KB L1 caches on Core, with a similar latency. AMD’s K8 also used an on-die memory controller, lowering memory latency significantly, despite the faster FSB of Intel Core (relative to Netburst) giving a lower latency to Core. As stated in our microarchitecture overview at the time, Athlon 64 X2s memory advantage had gotten smaller, but a key element to the story is that these advantages were negated by other memory sub-system metrics, such as prefetching. Measured by ScienceMark, the Core microarchitecture’s L1 cache delivers 2x bandwidth, and the L2 cache is about 2.5x faster, than the Athlon one.

Ten Year Anniversary of Core 2 Duo and Conroe Core: Decoding, and Two Goes Into One
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  • saratoga4 - Wednesday, July 27, 2016 - link

    >As we can see, by 2007 it was predicted that we would be on 10nm chips

    Should be 100 nm (0.1 microns).
    Reply
  • Jehab - Wednesday, July 27, 2016 - link

    Yeah, that is a massive error, lol. Reply
  • hammer256 - Wednesday, July 27, 2016 - link

    If I remember correctly, intel was running at 65nm in 2007 right? So I guess that was ahead of the curve at the time. Reply
  • JlHADJOE - Saturday, July 30, 2016 - link

    And the 2001 ITR roadmap actually predicted 22nm for 2016. Despite the delays getting to 14/16nm the industry is actually way ahead of the curve.

    http://www2.lbl.gov/Science-Articles/Archive/ALS-E...
    Reply
  • melgross - Wednesday, July 27, 2016 - link

    Exactly! I was going to post that myself. Once it's understood that it's actually 100nm, the other numbers make sense, otherwise, they don't. Reply
  • Walkermoon - Wednesday, July 27, 2016 - link

    Just signed up to say the same. Reply
  • Ian Cutress - Wednesday, July 27, 2016 - link

    Derp, I misread the table in a rush. Updated. Reply
  • Pissedoffyouth - Wednesday, July 27, 2016 - link

    Could you bench it against an AMD A10 Kaveri? That would be good Reply
  • Gc - Saturday, July 30, 2016 - link

    AMD A10-7800 (Kaveri) is in three of the bar charts on page 6. It appears to benefit from 4 cores in two of the comparisons. Reply
  • Zaxx420 - Wednesday, July 27, 2016 - link

    Still have a E8400 rig that I use every day...with it o/ced to 4GHz, 8gb of DDR2-1066 and a OCZ Vertex 2 SSD plus it's 6mb of cache on a P45 mobo...it can hold its own to this day...easily. The E8000 series is one of the best 'future proof' cpus ever...next up imo will prove to be Sandy Bridge. Have a 2500K at 4.5GHz on a Z68 mobo, 16gb DDR3-2400 and a Samsung 850 Pro ssd...and now a GTX 1060...plays any game I want at 1080 and max quality...easily. Reply

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