Core: It’s all in the Prefetch

In a simple CPU design, instructions are decoded in the core and data is fetched from the caches. In a perfect world, such as the Mill architecture, the data and instructions are ready to go in the lowest level cache at all times. This allows for the lowest latency and removes a potential bottleneck. Real life is not that rosy, and it all comes down to how the core can predict what data it needs and has enough time to drag it down to the lowest level of cache it can before it is needed. Ideally it needs to predict the correct data, and not interfere with memory sensitive programs. This is Prefetch.

The Core microarchitecture added multiple prefetchers in the design, as well as improving the prefetch algorithms, to something not seen before on a consumer core. For each core there are two data and one instruction prefetchers, plus another couple for the L2 cache. That’s a total of eight for a dual core CPU, with instructions not to interfere with ‘on-demand’ bandwidth from running software.

One other element to the prefetch is tag lookup for cache indexing. Data prefetchers do this, as well as running software, so in order to avoid a higher latency for the running program, the data prefetch uses the store port to do this. As a general rule (at least at the time), loads happen twice as often as stores, meaning that the store port is generally more ‘free’ to be used for tag lookup by the prefetchers. Stores aren’t critical for most performance metrics, unless the system can’t process stores quickly enough that it backs up the pipeline, but in most cases the rest of the core will be doing things regardless. The cache/memory sub-system is in control for committing the store through the caches, so as long as this happens eventually the process works out.

Core: More Cache Please

Without having access to a low latency data and instruction store, having a fast core is almost worthless. The most expensive SRAMs sit closest to the execution ports, but are also the smallest due to physical design limitations. As a result, we get a nested cache system where the data you need should be in the lowest level possible, and accesses to higher levels of cache are slightly further away. Any time spent waiting for data to complete a CPU instruction is time lost without an appropriate way of dealing with this, so large fast caches are ideal. The Core design, over the previous Netburst family but also over AMD’s K8 ‘Hammer’ microarchitecture, tried to swat a fly with a Buick.

Core gave a 4 MB Level 2 cache between two cores, with a 12-14 cycle access time. This allows each core to use more than 2MB of L2 if needed, something Presler did not allow. Each core also has a 3-cycle 32KB instruction + 32KB data cache, compared to the super small Netburst, and also supports 256 entries in the L1 data TLB, compared to 8. Both the L1 and L2 are accessible by a 256-bit interface, giving good bandwidth to the core.

Note that AMD’s K8 still has a few advantages over Core. The 2-way 64KB L1 caches on AMD’s K8 have a slightly better hit rate to the 8-way 32KB L1 caches on Core, with a similar latency. AMD’s K8 also used an on-die memory controller, lowering memory latency significantly, despite the faster FSB of Intel Core (relative to Netburst) giving a lower latency to Core. As stated in our microarchitecture overview at the time, Athlon 64 X2s memory advantage had gotten smaller, but a key element to the story is that these advantages were negated by other memory sub-system metrics, such as prefetching. Measured by ScienceMark, the Core microarchitecture’s L1 cache delivers 2x bandwidth, and the L2 cache is about 2.5x faster, than the Athlon one.

Ten Year Anniversary of Core 2 Duo and Conroe Core: Decoding, and Two Goes Into One


View All Comments

  • patel21 - Thursday, July 28, 2016 - link

    Me Q6600 ;-) Reply
  • nathanddrews - Thursday, July 28, 2016 - link

    Me too! Great chip! Reply
  • Notmyusualid - Thursday, July 28, 2016 - link

    Had my G0 stepping just as soon as it dropped.

    Coming from a high freq Netburst, I was thrown back, by the difference.

    Since then I've bought Xtreme version processors... Until now, its been money well spent.
  • KLC - Thursday, July 28, 2016 - link

    Me too. Reply
  • rarson - Thursday, August 4, 2016 - link

    I built my current PC back in 2007 using a Pentium Dual Core E2160 (the $65 bang for the buck king), which easily overclocked to 3 GHz, in an Abit IP35 Pro. Several years ago I replaced the Pentium with a C2D E8600. I'm still using it today. (I had the Q9550 in there for a while, but the Abit board was extremely finnicky with it and I found that the E8600 was a much better overclocker.) Reply
  • paffinity - Wednesday, July 27, 2016 - link

    Merom architecture was good architecture. Reply
  • CajunArson - Wednesday, July 27, 2016 - link

    To quote Gross Pointe Blank: Ten years man!! TEN YEARS! Reply
  • guidryp - Wednesday, July 27, 2016 - link

    Too bad you didn't test something with a bit more clock speed.

    So you have ~2GHz vs ~4GHz and it's half as fast on single threaded...
  • Ranger1065 - Wednesday, July 27, 2016 - link

    I owned the E6600 and my Q6600 system from around 2008 is still running. Thanks for an interesting and nostalgic read :) Reply
  • Beany2013 - Wednesday, July 27, 2016 - link

    Built a Q6600 rig for a mate just as they were going EOL and were getting cheap. It's still trucking, although I suspect the memory bus is getting flaky. Time for a rebuild, methinks.

    And a monster NAS to store the likely hundreds of thousands of photos she's processed on it and which are stuck around on multiple USB HDDs in her basement.

    It's not just CPUs that have moved on - who'd have thought ten years ago that a *good* four bay NAS that can do virtualisation would be a thing you could get for under £350/$500 (QNAP TS451) without disks? Hell, you could barely build even a budget desktop machine (just the tower, no monitor etc) for that back then.

    God I feel old.

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