Inside the Beast(s)

When the POWER8 was first launched, the specs were mind boggling. The processor could decode up to 8 instructions, issue 8 instructions, and execute up to 10 and all this at clockspeed up to 4.5 GHz. The POWER8 is thus an 8-way superscalar out of order processor. Now consider that

  1. The complexity of an architecture generally scales quadratically with the number of "ways" (hardware parallelism)
  2. Intel's most advanced architecture today - Skylake - is 5-way

and you know this is a bold move. If you superficially look at what kind of parallelism can be found in software, it starts to look like a suicidal move. Indeed on average, most modern CPU compute on average 2 instructions per clockcycle when running spam filtering (perlbench), video encoding (h264.ref) and protein sequence analyses (hmmer). Those are the SPEC CPU2006 integer benchmarks with the highest Instruction Per Clockcycle (IPC) rate. Server workloads are much worse: IPC of 0.8 and less are not an exception.

It is clear that simply widening a design will not bring good results, so IBM chose to run up to 8 threads simultaneously on their core. But running lots of threads is not without risk: you can end up with a throughput processor which delivers very poor performance in a wide range of applications that need that single threaded speed from time to time.

The picture below shows the wide superscalar architecture of the IBM POWER8. The image is taken from the white paper "IBM POWER8 processor core architecture", written by B. Shinharoy and many others.

The POWER8+ will have very similar microarchitecture. Since it might have to face a Skylake based Xeon, we thought it would be interesting to compare the POWER8 with both Haswell/Broadwell as Skylake.

The second picture is a very simplified architecture plan that we adapted from an older Intel Powerpoint presentation about the Haswell architecture, to show the current Skylake architecture. The adaptations were based on the latest Intel optimization manuals. The Intel diagram is much simpler than the POWER8's but that is simply because I was not as diligent as the people at IBM.

It is above our heads to compare the different branch prediction systems, but both Intel and IBM combine several different branch predictors to choose a branch. Both make use of a very large (16 K entries) global branch history table. Both processors scan 32 bytes in advance for branches. In case of IBM this is exactly 8 instructions. In case of Intel this is twice as much as it can fetch in one cycle (16 Bytes).

On the POWER8, data is fetched from the L2-cache and then predecoded into the L1-cache. Predecoding includes adding branch, exception, and grouping. This makes sure that predecoding is out the way before the actual computing ("Von Neuman Cycle") starts.

In Intel Haswell/Skylake, instructions are only predecoded after they are fetched. Predecoding performs macro-op fusion: fusing two x86 instructions together to save decode bandwidth. Intel's Skylake has 5 decoders and up to 5 µop instructions are sent down the pipelines. The current Xeon based upon Broadwell has 4 decoders and is limited to 4 instructions per clock. Those decoded instructions are sent into a µ-op cache, which can contain up to 1536 instructions (8-way), about 100 bits wide. The hitrate of the µop cache is estimated at 80-90% and up to 6 µops can be dispatched in that case. So in some situations, Skylake can run 6 instructions in parallel but as far as we understand it cannot sustain it all the time. Haswell/Broadwell are limited to 4. The µop cache can - most of the time - reduce the branch misprediction penalty from 19 to 14.

Back to the POWER8. Eight instructions are sent to the IBM POWER8 fetch buffer, where up 128 instructions can be held for two thread(s). A single thread can only use half of that buffer (64 instructions). This method of allocation gives each of two threads as much resources as one (i.e. no sharing), which is one of the key design philosophies for the POWER8 architecture.

Just like in the x86 world, the decoding unit breaks down the more complex RISC instructions into simpler internal instructions. Just like any modern Intel CPU, the opposite is also possible: the POWER8 is capable of fusing some combinations of 2 adjacent instructions into one instruction. Saving internal bandwidth and eliminating branches is one of the way this kind of fusion increases performances.

Contrary to the Intel's unified queue, the IBM POWER has 3 different issue queues: branch, condition register, and the "Load/Store/FP/Integer" queue. The first two can issue one instruction per clock, the latter can send off 8 instructions, for a combined total of 10 instructions per cycle. Intel's Haswell-Skylake cores can issue 8 µops per cycle. So both the POWER8 and Intel CPU have more than ample issue and execution resources for single threaded code. More than one thread is needed to really make use of all those resources.

Notice the difference in focus though. The Intel CPU has half of the load units (2), but each unit has twice the bandwidth (256 bit/cycle). The POWER8 has twice the amount of load units (4), but less bandwidth per unit (128 bit per cycle). Intel went for high AVX (HPC) performance, IBM's focus was on feeding 2 to 8 server threads. Just like the Intel units, the LSUs have Address Generation Units (AGUs). But contrary to Intel, the LSUs are also capable of doing simple integer calculations. That kind of massive integer crunching power would be a total waste on the Intel chip, but it is necessary if you want to run 8 threads on one core.

A POWER8 for Everyone Comparing with Intel's best
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  • tipoo - Thursday, July 21, 2016 - link

    They made PowerPC Windows? Source? I remember the Powermac G5s were the early dev kits for the xbox 360 due to the architecture similarity, but I assumed those stories meant they were just working in OSX or Linux on them.
  • thunderbird32 - Thursday, July 21, 2016 - link

    AFAIK, the last build of Windows for PPC was NT 4. So, it's been a while.
  • Sunner - Thursday, July 21, 2016 - link

    There were early builds of Windows 2000 for the RISC's as well, during the times when it was still called NT5. I had one of those from WinHEC, but alas I lost it when moving at some point. :(
  • yuhong - Thursday, July 21, 2016 - link

    AFAIK, the little endian PowerPC mode that NT4 used was killed when they went to 64-bit and is different from today's POWER8 little endian mode that was only recently introduced.
  • Kevin G - Thursday, July 21, 2016 - link

    I used to have such a disc for Windows NT4. That disk also had binaries for DEC Alpha and MIPS.
  • BillyONeal - Thursday, July 21, 2016 - link

    The Xbox 360 is a PPC machine, and runs a (heavily modified) version of Windows. My understanding is that most x86 assumptions had to be ferreted out to run on Itanium (early) and then on ARM (later).
  • Einy0 - Thursday, July 21, 2016 - link

    MS has builds that will run on anything. The real question is why would you want to? These chips are designed from the ground up to run massive work loads. It's a completely different style of computing than a Windows machine. Even MS server OSes aren't designed for this type of work. We are talking Banking, ERP and other big data applications. MS is still dreaming about scaling on that level. Right now their answer is clustering but that comes with it's own obstacles too.
  • abufrejoval - Thursday, August 4, 2016 - link

    Well there is always QEMU.

    And IBM has a much better binary translator from when they bought QuickTransit. That one originally translated Power to x86 for the Mac, then Sparc to x86 for Quicktransit and eventually x86 to Power for IBM so they could run Linux workloads on AIX.

    Then what exactly do you mean with Windows (assuming this is actually a reasonable question)?

    Server applications or desktop?

    .NET has been ported to Linux and I guess could be made to run on Power. A Power runtime could certainly be done by Microsoft, if they wanted to.

    I don't see why anyone would want to run Windows desktop workloads on this hardware, other than to show that it can be done: QEMU to that!
  • BedfordTim - Thursday, July 21, 2016 - link

    I was intrigued to see how little effect hyper-threading with your Xeon. My own experience is that it gives a 50% boost although I appreciate there are many variables.
  • Taracta - Thursday, July 21, 2016 - link

    Something seems to be wrong with the Mem Hierarchy charts in the Intel L3 and 16MB section.

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