Assessing IBM's POWER8, Part 1: A Low Level Look at Little Endian
by Johan De Gelas on July 21, 2016 8:45 AM ESTComparing with Intel's Best
Comparing CPUs in tables is always a very risky game: those simple numbers hide a lot of nuances and trade-offs. But if we approach with caution, we can still extract quite a bit of information out of it.
| Feature | IBM POWER8 |
Intel Broadwell (Xeon E5 v4) |
Intel Skylake |
| L1-I cache Associativity |
32 KB 8-way |
32 KB 8-way |
32 KB 8-way |
| L1-D cache Associativity |
64 KB 8-way |
32 KB 8-way |
32 KB 8-way |
| Outstanding L1-cache misses | 16 | 10 | 10 |
| Fetch Width | 8 instructions | 16 bytes (+/- 4-5 x86) | 16 bytes (+/- 4-5 x86) |
| Decode Width | 8 | 4 µops | 5-6* µops (*µop cache hit) |
| Issue Queue | 64+15 branch+8 CR = 87 |
60 unified | 97 unified |
| Issue Width/Cycle | 10 | 8 | 8 |
| Instructions in Flight | 224 (GCT SMT-8 modus) | 192 (ROB) | 224 (ROB) |
| Archi regs Rename regs |
32 (ST), 2x32 (SMT-2) 92 (ST), 2x92 (SMT-2) |
16 168 |
16 180 |
| Load Bandwidth (per unit) Load Queue Size |
4 per cycle 16B/cycle 44 entries |
2 per cycle 32B/cycle 72 entries |
2 per cycle 32B/cycle 72 entries |
| Store Bandwidth Store Queue Size |
2 per cycle 16B/cycle 40 entries |
1 per cycle 32B/cycle 42 entries |
1 per cycle 32B/cycle 56 entries |
| Int. Pipeline Length |
18 stages |
19 stages |
19 stages 14 stage from µop cache |
| TLB | 2048 4-way |
128I + 64D L1 1024 8-way |
128I + 64D L1 1536 8-way |
| Page Support | 4 KB, 64 KB, 16 MB, 16 GB | 4 KB, 2/4 MB, 1 GB | 4 KB, 2/4 MB, 1 GB |
Both CPUs are very wide brawny Out of Order (OoO) designs, especially compared to the ARM server SoCs.
Despite the lower decode and issue width, Intel has gone a little bit further to optimize single threaded performance than IBM. Notice that the IBM has no loop stream detector nor µop cache to reduce branch misprediction. Furthermore the load buffers of the Intel microarchitecture are deeper and the total number of instructions in flight for one thread is higher. The TLB architecture of the IBM POWER8 has more entries while Intel favors speedy address translations by offering a small level one TLB and a L2 TLB. Such a small TLB is less effective if many threads are working on huge amounts of data, but it favors a single thread that needs fast virtual to physical address translation.
On the flip side of the coin, IBM has done its homework to make sure that 2-4 threads can really boost the performance of the chip, while Intel's choices may still lead to relatively small SMT related performance gains in quite a few applications. For example, the instruction TLB, µop cache (Decode Stream Buffer) and instruction issue queues are divided in 2 when 2 threads are active. This will reduced the hit rate in the micro-op cache, and the 16 byte fetch looks a little bit on the small side. Let us see what IBM did to make sure a second thread can result in a more significant performance boost.
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JohanAnandtech - Thursday, July 28, 2016 - link
Ah, you will have to wait for the improved P8 which is the first Power going after HPC :-)RISC is RISKY! - Tuesday, August 2, 2016 - link
I would support "Brutalizer". Every processor has its strength and weakness. If memory architecture is considered, for the same capacity, Intel is conjested memory, IBM is very distributed and Oracle-Sun is something in between. So Intel will always have memory B/W problem every way. IBM has memory efficiency problem. Oracle in theory doesn't have problem, but with 2 dimm per ch, that look like have problem. Oracle-Sun is for highly branched workload in the real world. Intel is for 1T/Core more of single threaded workloads and IBM is for mixed workloads with 2T-4T/Core priority. So supercomputing workloads will work fast on IBM now, compared to intel and sparc, while analytics and graph and other distributed will work faster on SPARC M7 and S7 (although S7 is resource limited). While for intel, a soft mix of applications and highly customized os is better. Leave the business decisions and the sales price. List prices are twice as much as sales price in the real world. These three processors (xeon e5v4, power8-9, sparc m7-s7) are thoroughly tuned for different work spaces with very little overlap. So there's no point in comparing them other than their specs. Its like comparing a falcon and a lion and a swordfish. Their environments are different even though all of them hunt. Thats in the real world. So benchmarks are not the real proof. We at the university of IITD have lots and lots of intel xeon e5v4, some P8 (10-15 single and dual sockets), and a very few (1-2 two socket M7 and 2 two socket S7). We run anything and every thing on any of these, we get our hands on. And this is the real world conclusion. So don't fight. Its a context centric supply.RISC is RISKY! - Tuesday, August 2, 2016 - link
of processors!rootvgnet - Friday, August 12, 2016 - link
Johan - interesting article, I enjoyed it - especially after I discovered how to get to the next page.As far as the comments go - 1) a good article will get a diverse response (from those with an open, read querying, mind.
2) I agree with those who, in other words are saying: "there is no 'one size fits all'." And my gut reaction is that you are providing a level of detail that assists in determining which platform/processor "fits my need"
Looking forward to part2.