Today Imagination launches three new MIPS processor IPs: One in the performance category of Warrior CPUs, the P6600 and two embedded M-class core, the M6200 and M6250.

Warrior P6600

Starting off with the P6600, this is Imagination's new MIPS flagship core succeeding the P5600. The P5600 was a 3-wide out-of-order design with a pipeline depth of up to 16 stages. The P6600 keeps most of the predecessor's characteristics such as the main architectural features or full hardware virtualization and security through OmniShield, but adds compatibility for MIPS64 64-bit processing on top. Imagination first introduced a mobile oritented 64-bit MIPS CPU back with the I6400 a little more than a year ago but we've yet to see vendors announce products with it. 

We're still lacking any details on the architectural improvements of the P6600 over the P5600 so it seems that for now we're left with guessing what kind of performance the new core will bring. The P5600 was directly competing with ARM's Cortex A15 in terms of IPC, but ARM has since then not only announced but also seen silicon with two successor IPs to the A15 (A57 and A72), so the P6600 will have some tough competition ahead of itself once it arrives in products.

The P6600, much like the P5600 can be implemented from single-core to six-core cluster configurations. What is interesting that as opposed to ARM CPU IP, the MIPS cores allow for asynchronous clock planes between the individual cores if the vendors wishes to implement the SoC's power management in this way (It can also be set up to work in a synchronous way).

"MIPS P6600 is the next evolution of the high-end MIPS P-class family and builds on the 32-bit P5600 CPU. P6600 is a balanced CPU for mainstream/high-performance computing, enabling powerful multicore 64-bit SoCs with optimal area efficiency for applications in segments including mobile, home entertainment, networking, automotive, HPC or servers, and more. Customers have already licensed the P6600 for applications including high-performance computing and advanced image and vision systems."

Warrior M6200 & M6250

Also as part of today's announcement we see two new embedded CPU cores, the M6200 and M6250. Both cores are successors to the microAptiv-UP and UC but able to run at up to 30% higher frequency. The new processors also see an ISA upgrade to MIPS32 Release 6 instead of Release 5.

The M6200 is targeted at real-time embedded operating systems with minimal funtionality for cost- and power-savings. It has no MMU and as such can only be described as a microcontroller part.

The M6250 is the bigger brother of the M6200 and the biggest difference is the inclusion of a memory management unit (MMU) that makes this a full fledged processor core that can run operating systems like Linux.

"M6200 and M6250 are configurable and fully synthesizable solutions for devices requiring a high level of performance efficiency and small silicon area including wireless or wired modems, GPU supervisors, flash and SSD controllers, industrial and motor control, advanced audio and more."

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  • KateH - Tuesday, November 10, 2015 - link

    Kind of a shame that high-end MIPS hasn't taken off (well, returned I guess- I had MIPS-based SGI workstations in the early 2000's), these are interesting designs. P6600 with 6C/24T would be a low-power beast if there was software for the platform. Reply
  • jospoortvliet - Tuesday, November 10, 2015 - link

    There is just too much competition. Intel, ARM and OpenPOWER leave little room... Reply
  • SarahKerrigan - Tuesday, November 10, 2015 - link

    I would call Broadcom's XLP II (20 cores, 2+ GHz, 4-issue out-of-order, 4-threaded SMT) pretty high end. It just doesn't use licensed cores. Reply
  • alexvoica - Tuesday, November 10, 2015 - link

    There are several high-end SoCs using MIPS, including Broadcom and Cavium (mentioned below) but also the new Loongson-3A2000 and 3B2000.
    http://blog.imgtec.com/mips-processors/loongson-mi...

    We also have a new customer targeting the HPC space using MIPS64, more details coming soon.
    Reply
  • r3loaded - Tuesday, November 10, 2015 - link

    IMGTEC are gonna need some kind of USP or hook that gets vendors to overlook the different architecture and buy in, whether that's a low price, high performance or some useful feature not available in other architectures. Intel already has it covered on widespread adoption in laptops/desktops/server and performance-per-watt, ARM wins on power efficiency and in the mobile space (and is looking to move into ultra low-power IoT as well as servers), and POWER has the threading advantage and RAS features on high-end server systems.

    I'm not sure where MIPS can slot in in all of this.
    Reply
  • sseemaku - Tuesday, November 10, 2015 - link

    Are there any devices with MIPS CPUs? Considering the amount of investment that would have gone to make these cores, they will need good design wins. Reply
  • MrMilli - Tuesday, November 10, 2015 - link

    Cavium and Broadcom used to be big proponents of the MIPS architecture, having their own MIPS designed cores, but both have switched to ARM.
    You can find a lot of MIPS cores in wireless and networking controllers.
    Reply
  • A5 - Tuesday, November 10, 2015 - link

    Cavium is still making new MIPS cores, I know.

    The thing with MIPS is that the per-thread performance is poor, so it is good if you just need a ton of light-weight threads but isn't competitive with even ARM or PPC if your sw arch doesn't take advantage of what they're good at.
    Reply
  • MrMilli - Tuesday, November 10, 2015 - link

    Maybe true for what Cavium makes but the P5600 is supposed to have very good single threaded performance.

    http://blog.imgtec.com/mips-processors/mips-p5600-...
    http://blog.imgtec.com/multimedia/the-day-i-design...

    I guess the 'competing CPU IP' is an A15 which would put the P5600 in A57 Coremark/Mhz ballpark. I think the reason we're not seeing any competitive SOC with Warrior IP is software. It took Google way too long to really get MIPS (and x86 for that matter) well implemented into the Android NDK.
    Reply
  • alexvoica - Tuesday, November 10, 2015 - link

    Ian wrote an article about the new Baikal-T1 using a dual-core MIPS P5600.
    http://www.anandtech.com/show/9285/spot-the-cpu-ru...
    Reply

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