An increase to L1 TLB Entries

The first advantage the Athlon 4 offers is an increase in the number of L1 translation lookaside buffer (TLB) entries. When a processor accesses main memory it doesn't directly reference the physical addresses in memory. Instead there is a set of virtual addresses that map onto these physical addresses in memory. The process of translating virtual addresses to physical addresses is necessary for actually getting to data in main memory. Unfortunately, your CPU doesn't like to have to go to main memory. The reason being that when your CPU must go to main memory it has to travel down the FSB, through the North Bridge and down the memory bus before it can actually get to the main memory. A way of avoiding this long trip is by caching.

You all are aware of two particular types of processor caches, the L1 and L2 caches. These caches can store frequently used data. Well, there is also another type of a cache known as the Translation Lookaside Buffer or TLB for short. The TLB caches the translated addresses that result from this virtual address to physical address translation process. The probability of a CPU finding the address it needs in its TLB is extremely high, usually on the order of 99%; this is known as the processor's TLB hit-rate. This is quite good since in the event that the CPU cannot find an address it needs in the TLB, the penalty can be incredible and the CPU's performance suffers in turn. In order to resolve a single address the penalty can be 3 clock cycles. Multiply that by the number of addresses that must be looked up in main memory and you can see where the CPU would end up slowing down considerably because of this. Upon a hit to the TLB this lookup can be done in 1 clock cycle, improving performance by 200%.

The TLB for the L1 cache on the Athlon 4 has received an increase in the number of entries, which increases the hit rate for the Athlon's TLB. The Thunderbird only had a 24-entry L1 TLB compared to the 32-entry L1 TLB on the Pentium III for the instruction cache and a 32-entry TLB for the L1 data cache as opposed to the Pentium III's 72-entry L1 D-cache TLB; Unfortunately AMD did not have the exact number of L1 TLB entries of the Athlon 4. We simply know that they did increase the number.

This increase actually only amounts to a marginal real-world performance increase for the Athlon 4 over the Athlon (Thunderbird) so you shouldn't get too excited over it.

The Technology behind Athlon 4 Data Prefetch

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