Each Bulldozer module consists of two cores, so two cores is most likely the minimum you can use.

It is 1 core. These so called modules are AMD marketing terminology for actual cores. The two logical cores are from AMD's SMT implementation. Unfortunately, it does not seem like it is possible to turn that off to get 1 logical core.

That is a grossly misinterpretation of the truth. Each module still has 2 integer cores and many components are doubled. It is DEF not SMT, Sure the FPU is shared but even then its a 4 FPU core CPU. No excuse for benchmarks below a Phenom core per core.

CMT for integer workloads, SMT for floating point.

"CMT" Like Country Music Television?

Sorry, SMT is Symetric Multi Threading, useful for integer or FP multithreading.

A single Bulldozer module will fully multithread integer caluclations and up to 128 bit SIMD (Single Instruction, Multiple Data) and FP instructions. (Standard FP calculations are 64 or 80 bit.) The only point where it will only handle one thread per module is 256 bit SIMD instructions. The big downside is that the x86 instruction converter/scheduler only handles 4 instructions per clock. That's primarily holding back the BD performance. If they could get that up to 8, it would match the current Phenom II architecture. If they could get it up to 12 and shorten the execution pipeline, I bet it might even match SB.

Never heard of CMT other than the cable channel.

CMT = cluster multi-threading.

conroe, wolfdale, nehalem and sandy bridge all decode a max of 4 instructions per clock, per core. nehalem and SB share that between two threads per core.
K-8, K-10 and K-10.5 can decode 3 instrctions per clock, per core. no sharing.
buldozer decodes 4 instructions per module shared between 2 integer cores. it doesn't need an 8 wide decoder- it would be HUGE! bulldozer also has the same pipline length(roughly) as nehalem/SB. so thats fine.
the issue is in the cache speed/latency, OoO buffers(too small compared to nehalem and SB) and i would surmise the the 'fusion ops' isn't as good as what intel implements- thats huge.
a 3rd alu added per integer core would help, though. but thats going to increase the size, too and create executions resources that would go unused in some instances.
silverblue is right- 'cluster multi-threading'. sun micro-systems(now oracle) used it on the sparc and ultra-sparc processors.

So that means Intel 990X chips have 12 cores then? Because i7's have the same stuff.

Subject Comment

Please login or register to post a comment.
User Name Password