IDF CPU Report - Intel & AMD

Grasping the architectural advantages of the Willamette may be a difficult feat to accomplish, but for most of the IDF attendants, learning how to pronounce the code name of the upcoming processor was even more challenging.  For starters, the name Willamette (taken from a river near where the CPU was designed), is pronounced Will-AM-ette.  But now to the more important things ;)

Willamette will be Intel’s first major architectural change since the Pentium Pro was introduced seemingly ages ago, in 1995.  What all is a part of this “major architectural change” that we keep on talking about? 

By increasing the pipeline of the Willamette (up from 10-stages on the Pentium III) Intel is able to increase the clock speed of the Willamette.  How can increasing the pipeline to 20 stages allow for higher clock speeds?  By increasing the length of the pipeline, less is done in a single clock cycle meaning that the CPU can operate at a higher frequency whereas with a shorter pipeline, where more is done in a single clock cycle (more complex work per clock) you are limited to lower clock frequencies. 

Since the Willamette is geared to be the successor to the Pentium III (which is the reasoning behind most people referring to it as the Pentium IV), it makes perfect sense that Intel would want to debut it at a higher clock speed than the Pentium III.  With the current Pentium III Coppermine core to hit 1GHz around the launch, this clock speed advantage is absolutely necessary because otherwise it would be difficult for Intel to demonstrate any purpose for the Willamette if it weren’t clocked noticeably higher than the Pentium III.  Remember, since the Willamette probably can’t do as much per clock as the Athlon/Pentium III it will rely on this increased clock speed to remain competitive. 

As the clock speed increases beyond what the Pentium III would be able to accomplish, something that is made possible because of the deeper pipeline, the Willamette’s 20 stage pipeline will truly begin to shine.

In essence, the number of pipeline stages you have helps to determine the attainable clock speed of your processor, the deeper the pipeline, the higher your clock speed can go. 

Modern day CPUs attempt to increase the efficiency of their pipelines by predicting what they will be asked to do next, this is a simplified explanation of the term Branch Tree Prediction.  When a processor predicts correctly, everything goes according to plan but when an incorrect prediction is made the processing cycle must start all over at the beginning of the pipeline.  Because of this, a processor with a 10 stage pipeline has a lower penalty for a mis-predicted branch than that of a processor with a 20 stage pipeline.  The longer the pipeline, the further back in the process you have to start over in order to make up for a mis-predicted branch.

With the Willamette boasting a 20 stage pipeline, the penalty for a mis-predicted branch is much greater than it would be on a Pentium III.  So how did Intel attempt to work around this problem?