Words of Thanks

Many people gave us assistance with this project, and we would of course like to thank them.

Trevor Lawless, Intel US
Sanjay Sharma, Intel US
Matty Bakkeren, Intel Netherlands
(www.intel.com)

Damon Muzny, AMD US
Joshua Mora, AMD US
Brett Jacobs, AMD US
(www.amd.com)

Randy Chang, ASUS
(www.asus.com)

Kelly Sasso, Crucial Technology

Benchmark configuration

Here is the list of the different configurations. We flashed all servers to the latest BIOS, and unless we add any specific comments to the contrary, the BIOS are set to default settings.

Xeon Server 1: Intel "Stoakley platform" server
Supermicro X7DWE+/X7DWN+ Bios rev 1.0
2x Xeon E5472 at 3GHz
8GB (4x2GB) Crucial Registered FB-DIMM DDR2-667 CL5 ECC
NIC: Dual Intel PRO/1000 Server NIC

Xeon Server 2: Intel "Bensley platform" server
2x Xeon E5365 at 3GHz or 2x Xeon E5345 at 2.33GHz
Intel Server Board S5000PSL - Intel 5000P Chipset
8GB (4x2GB) Crucial Registered FB-DIMM DDR2-667 CL5 ECC
NIC: Dual Intel PRO/1000 Server NIC

Opteron 2350 Server: ASUS KFSN4-DRE
Dual Opteron 2350 2GHz
Asus KFSN4DRE BIOS version 1001.02 (8/28/2007) - NVIDIA nForce Pro 2200 chipset
8GB (4x2GB) Crucial Registered DDR2-667 CL5 ECC
NIC: Broadcom BCM5721

Opteron Socket F 1207 Server: Tyan Transport TA26 - 2932
Dual Opteron 2222 3GHz/2224SE 3.2GHz
Tyan Thunder n3600m (S2932) - NVIDIA nForce Pro 3600 chipset
8GB (4x2GB) Crucial Registered DDR2-667 CL5 ECC
NIC: nForce Pro 3600 integrated MAC with Marvell 88E1121 Gigabit Ethernet PHY

Client Configuration: Dual Opteron 850
MSI K8T Master1-FAR
4x512MB Infineon PC2700 Registered, ECC
NIC: Broadcom 5705

OS Software
64-bit SUSE Linux SLES 10 SP1 (Linux 2.6.16.46-smp x86_64)
32-bit Windows 2003 Enterprise SP1

The Opteron 2360SE - the Facts The memory subsystem (Linux 64-bit)
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  • befair - Friday, November 28, 2008 - link

    ok .. getting tired of this! Intel loving Anandtech employs very unfair & unreasonable tactics to show AMD processors in bad light every single time. And most readers have no clue about the jargon Anandtech uses every time.

    1 - HPL needs to be compiled with appropriate flags to optimize code for the processor. Anandtech always uses the code that is optimized for Intel processors to measure performance on AMD processors. As much as AMD and Intel are binary compatible, when measuring performance even a college grad who studies HPC knows the code has to be recompiled with the appropriate flags

    2 - Clever words: sometimes even 4 GFLOPS is described as significant performance difference

    3- "The Math Kernel Libraries are so well optimized that the effect of memory speed is minimized." - So ... MKL use is justified because Intel processors need optimized libraries for good performance. However, they dont want to use ACML for AMD processors. Instead they want to use MKL optimized for Intel on AMD processors. Whats more ... Intel codes optimize only for Intel processors and disable everything for every other processors. They have corrected it now but who knows!! read here http://techreport.com/discussions.x/8547">http://techreport.com/discussions.x/8547

    I am not saying anything bad about either processor but an independent site that claims to be fair and objective in bringing facts to the readers is anything but fair and just!!! what a load!
    Reply
  • DonPMitchell - Friday, December 07, 2007 - link

    I think a lot of us are intrigued by AMD's memory architecture, its ability to support NUMA, etc. A lot of benchmarch test how fast a small application runs with a high cash-hit rate, and that's not necessarily interesting to everyone.

    The MySQL test is the right direction, but I'd rather see numbers for a more sophisticated application that utilizes multiple cores -- Oracle or MS SQL Server, for example. These are products designed to run on big iron like Unisys multi-proc servers, so what happens when they are running on these more economical Harpertown or Barcelona.
    Reply
  • kalyanakrishna - Thursday, November 29, 2007 - link

    http://scalability.org/?p=453">http://scalability.org/?p=453 Reply
  • kalyanakrishna - Thursday, November 29, 2007 - link

    a much better review than the original one. But I still see some cleverly put sentences, wish it were otherwise. Reply
  • Viditor - Thursday, November 29, 2007 - link

    Nice review Johan!

    On the steppimgs note you made, it's not the B2 stepping that is supposed to perform better, it's the BA stepping...
    The BA stepping was the improved form for B1s, and the B3 stepping is the improved form of the B2. BA and B2 came out at the same time in Sept (though BA was the one launched, B1 was what was reviewed), B2 for Phenom and performance clockspeeds, BA for standard and low power chips.
    Do you happen to have a BA chip to test (those are the production chips)?
    Reply
  • BitByBit - Wednesday, November 28, 2007 - link

    Despite K10's rather extensive architectural improvements, it looks likes its core performance isn't too different to K8. In fact, the gains we've seen so far could easily be attributable to the improved memory controller and increased cache bandwidth. It seems that introducing load reordering, a dedicated stack, improved branch prediction, 32B instruction fetch, and improved prefetching has had little impact, certainly far less than expected. The question is, why? Reply
  • JohanAnandtech - Wednesday, November 28, 2007 - link

    Well, we are still seeing 5-10% better integer performance on applications that are runing in the L2, so it is more than just a K8 with a better IMC. But you are right, I expected more too.

    However, the MySQL benchmark deserves more attention. In this case the Barcelona core is considerably faster than the previous generation (+ 25%). This might be a case where 32 bit fetch and load reordering are helping big time. But unfortunately our Codeanalyst failed to give all the numbers we needed
    Reply
  • BaronMatrix - Wednesday, November 28, 2007 - link

    At any rate, it was the most in-depth review I've seen, especially with the code analysis. I too, thought it would be higher, but remember that Barcelona is NOT HT3 and doesn't have the advantage of "gangning\unganging." There was an interesting article recently that showed perf CAN be improved by unganging (maybe it was ganging, can't find it) the HT3 links.

    I really hate that OEMs decided to stand up to the big, bad AMD and DEMAND that Barcelona NOT have HT3 with ALL OF ITS BENEFITS.

    I mean people complain that Barcelona uses more power, but HT3 would cut that somewhat. At least in idle mode, and even in cases where IMC is used more than the CPU or vice versa.


    I also may as well use this to CONDEMN all of these "analysts" who insist on crapping on the underdog that keeps prices reasonable and technology advancing.

    INSERT SEVERAL EXPLETIVES. REPEATEDLY. FOR A FEW DAYS. A WEEK. FOR A YEAR.

    INSERT MORE EXPLETIVES.
    Reply
  • donaldrumsfeld - Wednesday, November 28, 2007 - link

    Conjecture regarding why AMD went quad core on the same die... and this has nothing to do with performance. I think one place where Intel is way ahead of AMD is package technology. Remember they were doing a type of Multichip module with the P6. Having 2 dice instead of a single die allows them to have an overall lower defect rate, higher yield, and higher GHz. This is vs. AMD's lower GHz but (it was hoped) greater data efficiency using an L3 die and lower latency of on-die communications amongst cores vs. Intel's solution of die to die communication.

    Can anyone confirm/deny this?

    thanks
    Reply
  • tshen83 - Tuesday, November 27, 2007 - link

    Seriously, can you buy the 2360SE? Newegg doesn't even stock the 1.7Ghz 2344HEs.

    The same situation exist on the Phenom line of CPUs. I don't see the value of reviewing Phenom 9700, 9900s when AMD cannot deliver them. I have trouble locating Phenom 9500s.
    Reply

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