Intel Developer Forum 2007 - Day 1: More Nehalem, Penryn Announced, and Gelsinger Speaksby Anand Shimpi & Larry Barber on September 18, 2007 8:03 PM EST
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When we published today's initial coverage we gave Nehalem very short treatment, simply due to a lack of time, but now that things have slowed down a bit we can touch on the gravity of today's Nehalem demonstrations.
We've talked in the past about Intel's incredibly strong roadmap and how it's firing on all cylinders, today's demonstration is perfect indication of that. Penryn isn't even out the door yet and Nehalem is design-complete, undergoing testing and already running two major OSes according to Intel.
We've yet to lay our hands on AMD's Phenom, much less give you more than a crude set of performance expectations based on server hardware, needless to say Intel is doing to AMD, what AMD did to Intel for years while the Pentium 4 struggled to perform.
Let's say that again: Intel is showing an architecture that won't be out until the end of next year, today.
A mere four hours after the first Nehalem demo, Intel was back with another one and this one, even more impressive. Nehalem uses Intel's new QuickPath interconnect, formerly known as CSI, and a direct competitor to AMD's Hyper Transport. Doing away with the Front Side bus and implementing a point-to-point interconnect is a huge feature of Nehalem, especially for the enterprise market, and Intel's second demo showcased just that.
The second Nehalem system featured two quad-core Nehalem processors running in a two-socket system, the two sockets being connected via QuickPath.
Each quad-core Nehalem has SMT enabled, meaning each core can work on two threads simultaneously, so the entire box can simultaneously work on 16 threads as is evidenced by the obligatory task manager screenshot:
Obviously we have no performance data or clock speed information, we'd expect both to be quite low at this point but the fact that we're seeing the demo today is quite good. Despite worries of AMD being uncompetitive going forward, Intel seems to be proceeding according to plan, which is exactly what we want to see.
Nehalem will also add 7 new SSE4 instructions to its reportoire, note the diagram showing direct connections between processors and memory, very AMDesque
The Nehalem launch is a very important one for Intel as it is the first full repetition of its 2-year architectural cycle (tick-tock model); many wondered if Intel could pull it off, and we'll find out by this time next year.