Fall IDF 2005 - Day 2: More Details on VIIV and Next-Gen Architectureby Anand Lal Shimpi on August 24, 2005 7:21 PM EST
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We've got two items to update you all on, let's first start with some more information about Intel's next-generation microprocessor architecture.
There's a lot more than meets the eye when it comes to Intel's next-generation micro-architectures, but Intel is saving quite a bit of that for the Spring 2006 IDF. One feature that they did quietly introduce was something they call Memory Disambiguation, which we referred to in our previous article on the topic as speculative data loads.
We got a slightly better grasp on the feature, and it basically works like this:
Normally when an Out of Order microprocessor re-orders instructions, it cannot reschedule loads ahead of stores because it does not know if there are any dependencies it would be violating.
Intel's memory disambiguation technology is essentially speculative loading, where based on some algorithms the processor evaluates whether or not a load can be executed ahead of a store, if it can then the load instructions can be rescheduled to further optimize for the highest possible instruction level parallelism. If the speculative load ends up being valid, then business is as usual, otherwise the result must be thrown away and the load executed after the store is complete.
Intel couldn't provide us with more information on the speculative loading, in particular the accuracy of its speculative algorithms, but we would assume that they would be highly accurate if this technology will be used in mobile processors. Anything speculative has the potential to be a waste of power if not done with the highest accuracy.