IDF Spring 2005 - Predicting Future CPU Architecture Trendsby Anand Lal Shimpi on March 3, 2005 7:43 PM EST
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We've come across a lot of information about the future of Intel architectures and platforms during these past three days at IDF. We've taken this opportunity to summarize it as best as we can, so let's get started.
More thoughts on Stacked DRAM
Our own Johan De Gelas caught up with Justin Rattner after his keynote to get some more information about stacked die and wafer technology:
1) Current Intel research estimates that about 256MB of memory can be stacked on top of a CPU (die stacking). A huge latency reduction is the result, but if you need more memory you have to go off die of course.
2) Different thermal expansion between the layers might of course ruin the chip. Intel is looking into this but Justin believes that it is not going to stop the stacked die show.
3) Right now stacked die is obviously in its infancy, they still have to move to the next step: one memory chip on top the other.
We're quite excited about the possibility of stacked DRAM although it will definitely be a long time before we see it productized.