Introduction

We have been patiently waiting this Fall's Intel Developer Forum for quite some time. Rumors that Intel would host a live dual core demonstration have kept our interest piqued. It's tough to deal with that guilty kind of excitement, the kind where you hope for something you couldn't expect and the very hope itself seems to crush the chances of its fulfillment. After all the waiting, we can say that the rumors were true: Intel just finished demonstrating a running dual core Montecito Itanium processor. This is a good thing and a bad thing, but we'll talk more about that in a minute.



Amidst a few new things, we did hear plenty of the same old thing from Intel about technologies that are either here now, or years off into the future (with no new insight). For instance, much of the keynote covered Hyperthreading, EM64T, and Wifi, or focused on previously demonstrated technologies like Vanderpool. While all of these things are fun and interesting, we've already heard about them time and time again. Granted, the Vanderpool demo was from a business perspective rather than a home user perspective. It's cool to see 4 different hardware virtualized systems running on one computer, but the concept's potential and its uses have been explored previously via software such as VMWare. But buried in the presentation were a few tidbits we did find useful, and that's what where here to bring you today.

The following pages will cover the the new things mentioned at the opening keynote, as well as the growing importance Intel places on parallelism.
What's New From the Keynote
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  • IntelUser2000 - Tuesday, September 14, 2004 - link

    Ah crap. Posted empty message.

    Anyways, in response to:
    "That's what I like about the Athlon 64, no stupid large caches necessary"

    One major thing that people get wrong is that "Imagine Athlon64 or Opteron with 24MB cache". The thing is, AthlonXP and Opteron/Athlon64 didn't get much benefit from cache anyway as Pentium 4 did. We didn't see significant improvements going to Barton with 512KB L2 cache compared to P4, which had much larger performance improvements(Barton Link: http://www.anandtech.com/cpuchipsets/showdoc.aspx?... Pentium 4 Northwood Link: http://www.anandtech.com/cpuchipsets/showdoc.aspx?...

    Comment from Barton review at last page:"It is very interesting to note the relatively small performance improvement that resulted from the additional L2 cache, at least when you compare the impact of Barton to the impact Northwood had on the Pentium 4."

    If you look at the reviews, there are times where Barton is basically equal to the Thoroughbred B core, even considering that Thoroughbred B has 3.8% higher clock than Barton, doubling of L2 cache from 256KB to 512KB didn't do much as 512KB cache did on P4.

    So if AMD puts the current Itanium's 6MB L3, not only there won't be a significant performance increase, the performance scaling would rapidly decrease. That's the reason why S754 Sempron isn't much worse than full-blown Athlon64 with double L2 cache. So even if AMD has the resources or the will to put 6MB L2, it won't benefit Opteron/A64 much.

    Look at this link: http://www.anandtech.com/cpuchipsets/showdoc.aspx?...

    I mean, how can two processors that are targeted at such different markets, Sempron for value and A64 for mainstream, and cache size, have such little difference in performance? Why get A64 2800+ Newcastle when Sempron does same with 1/2 the price? So I say AMD will be lucky to get 10-15% performance increase by going to 24MB cache at this scaling.

    It's not the ability of AMD to put 24MB L2 or L3 cache that's the problem, its the performance that's squeezed out of that.

    Itaniums however(especially with Montecito), love bandwidth like Pentium 4's and Xeons and since Montecito is Dual-core, 2 thread per core(it's called Switch on Event Multithreading, which is different from Simultaneous Multithreading which Intel calls Hyperthreading), double the L2 cache of Madison9M's cache and some will be VERY useful.

    By the way, Montecito performance figures are 1.5x-2.0x PER core, with same 400MHz bus speed as Madison said here, and is rumored to have a version that's available with 18GB/sec FSB and memory bandwidth, from the current 6.4GB/sec: http://www.realworldtech.com/forums/index.cfm?acti...

    Thanks for reading(if you did anyway).
    Reply
  • IntelUser2000 - Tuesday, September 14, 2004 - link

    Reply
  • JarredWalton - Friday, September 10, 2004 - link

    #25 - I think I saw something from AMD that suggested that software should be licensed per socket in the future. Obviously, MS will do what they feel is in their best interest, but license fees per socket would be nice.

    #23 - There *are* drawbacks to having an integrated memory controller, and Hypertransport probably doesn't boost speed in single processor installations much at all. Anyway, Intel certainly has had some difficulties of late witht their CPU design. What I'm saying, though, is that their manufacturing facilities are probably the best around, with IBM coming in second.
    Reply
  • plk21 - Thursday, September 09, 2004 - link

    So, how will this affect Microsoft's Per Processor licensing on SQL Server? Will I have to buy 2 licenses per processor? Now I'm running it on Hypertrhreaded chips, only with 1 license per physical chip...
    Reply
  • PsharkJF - Thursday, September 09, 2004 - link

    #21
    I wasn't saying that Intel's helping them, I'm saying that Intel is being AMD's guinea pig :P
    #22
    ------
    One fine day Intel might come back with a vengeance and show us someting that beats the crap out of AMD64
    ------
    Dual pentium M with onboard memory controller *drool*
    Reply
  • ceefka - Thursday, September 09, 2004 - link

    What puzzles me is, when they are so "ahead of the game", why didn't they too come up with the idea of an onboard mem-controller and something like Hypertransport or Hypertransport itself? If you see what it does for AMD64's and Opterons, imagine what it could do for a Prescott or Xeon. No Sir, they just slap on extra cache, pump the FSB some more and leave the darn thing screaming for bandwith. In my view they are also a little complacent.

    One fine day Intel might come back with a vengeance and show us someting that beats the crap out of AMD64 or Opteron. That's what I've been thinking for almost 6 months now... If only AMD would sit still for a minute ;-)
    Reply
  • JarredWalton - Thursday, September 09, 2004 - link

    #21 - Actually, that's not at all correct, unless you think that Intel is sending over their people to help AMD out with getting their 90 nm up and running? IBM might do that, but not Intel. :p AMD is also still using 200 mm wafers, which is seriously behind the state of the art. Basically, AMD started investing in their 90 nm plant 2+ years ago, so they weren't waiting for Intel to have problems and work them out. They're starting construction of a 65 nm plant as well, which will finally get them 300 mm wafers. AMD still makes a great chip, but honestly Intel is ahead on several key areas of manufacturing technology. Reply
  • PsharkJF - Thursday, September 09, 2004 - link

    #13
    ------
    You can make a case for some issues with their designs of late, but as far as technology? We've seen 90 nm parts from Intel for almost a year now (more if you count early samples), while AMD is only just starting to ship them.
    ------
    In other words, AMD is playing it smart and letting Intel work out the kinks in the technology for them before they spend any money doing things that may not work well.
    Also consider that Intel needs smaller dies due to higher clockspeed requirements.
    Reply
  • 8NP4iN - Wednesday, September 08, 2004 - link


    the message is clear

    intel has failed
    Reply
  • PrinceGaz - Wednesday, September 08, 2004 - link

    I dread to guess at just how expensive those Montecito's with 1.7 billion transistors would cost. Probably quite a bit more than the $400 or so I'm looking to spend on my next CPU, I reckon :) Reply

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