Original Link: http://www.anandtech.com/show/3397

Raja and Kris have been busy in the labs working on ways to improve overclocking with the current X48, P45, and 790i chipsets. We are not looking at traditional methods like improved cooling methods, greater voltages, or handpicking components to give us the best possible results. Instead, we are taking a look at components utilized on current motherboards, speaking with the chipset design teams, and working with the BIOS engineers to determine the best possible way to improve clocking rates of not only the chipsets, but the processor and memory also.

As a result of this effort, we will publish a technical article on our first findings along with the motherboard modifications we implemented to improve both CPU and memory clocks without resorting to increased voltages or exotic cooling to improve the performance of off the shelf components. In the meantime, we are providing a glimpse today into the world of oscillators and PLL chips along with some preliminary memory clocking results.

First Results

Samsung is introducing new high speed DDR3 ICs that have been generating a lot of interest at the very high end. Corsair publicized stock and overclocked results with their upcoming CAS 9 spec DDR3-2133 kit recently. These particular speeds are impressive but also left us wondering what the Micron D9JNL part was truly capable of at CAS 8.

After making a few minor changes to the ASUS P5E3 Premium X48-based motherboard, we are able to operate our excellent Micron-based DDR3-1866 kit from Cell Shock at DDR3-2160, 8-8-8-24-2N with only 2.02V (actual). Our CPU voltage is 1.375V, 1.71V on the MCH, and PLL is set to 1.6V, significantly under voltage settings required on the Samsung kits at DDR3-2133 at 9-9-9-24-1N. These modifications work with a variety of memory kits from OCZ, Patriot, Corsair, and others at various speed ratings. This includes 2GB, 4GB, and 8GB configurations on standard BIOS releases with each kit seeing up to a 10% increase in clock speeds at tighter timings, all on reduced voltages compared to a stock board.

ASUS sent us a new BIOS that provides additional MCH clock skew settings (independent skew for each memory slot) that should allow us to go higher when overclocking 4GB or 8GB of memory. Also, we expect to see significant improvements with the new Samsung kits. We will provide full test results including application benchmark results in the coming article. In the meantime, here is some technical information behind the components we modified and why.

Tech Talk

Crystal oscillators are typically used to supply a reference frequency to a PLL (phase locked loop) which in turn feeds a clock signal to vital system components such as the CPU, memory, MCH, PCI and PCI/e busses. Most of these sub-systems are fed by individual PLL circuits. Each of these PLL sub-systems multiplies the base reference frequency supplied by the crystal oscillator by either a fixed or variable factor to obtain a final operating frequency for the bus in question.

The PLL compares the reference input clock frequency (supplied by the crystal oscillator) and phase to the output phase/frequency and applies adjustments via a negative feedback loop to ensure that the output clock signal maintains a reasonable accuracy. In an ideal world, the crystal oscillator would supply a perfect reference clock signal to the PLL, which in turn would generate a perfect time/frequency-aligned squarewave.

Unfortunately, things are far from ideal in the real world even with the clever usage of circuit topologies, as most of the affordable solutions all suffer from a common malady that can be reduced somewhat based upon the ingenuity of the PCB and power supply engineer. Optimizing ground plane trace layouts and keeping negative feedback paths as short as possible are some of the improvements that a good engineer will employ to help to reduce frequency errors of the output clock signal waveform.

However, even though feedback loops and PCB layout help to reduce output signal anomalies, the correction process itself is subject to a time delay before any applied corrective measure takes effect. Also bear in mind that the feedback loop relies on the quality of the input reference signal - any errors generated by the crystal oscillator (the small can shaped object in the image) will be superimposed onto the PLL output signal - the feedback loop cannot eliminate reference signal errors.

Factors such as radio interference and electro-magnetic interference from surrounding circuitry also impose their presence upon the clock signal adding further deviation from the desired resonating frequency. Finally, crystal oscillators are also susceptible to temperature related drift, heavily overclocked boards can be subjected to wide temperature swings depending upon the cooling used at key locations of the motherboard. These obstacles contribute towards random shifts of the clock signal waveform. This phenomenon is commonly known in the digital world as 'jitter'.

Reducing the level of jitter basically comes down to component cost and to a lesser 'workaround' extent - BIOS coding. Going the improved parts route does not always add up, crystal oscillators are priced and sold according to their time and temperature based drift (measured in parts per million) from the desired resonating frequency, though there is more to overall quality than PPM alone - again we need to look towards device jitter to determine the real value of the device in question. Naturally the lower Jitter parts cost more than the standard tolerance crystals, so designers rely on the built in clock skew registers of the MCH and in some instances the PLL chip itself to help align bus waveforms with one another so that data can be sampled accurately.

That is it for today. We will be back shortly with performance results and further technical details.

Gallery: Jitter Images

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