CPU feature |
Motorola G4+ |
G5 (IBM PowerPC 970) |
Intel Xeon P4 Irwindale |
AMD Opteron Troy |
Process technology |
0.18 µ CU SOI |
0.09 µ CU SOI |
0.09 µ CU |
0.09 µ CU SOI |
GP Register Width (bit) |
32 |
64 |
64 |
64 |
Number of transistors (Million) |
33 |
58 |
169 |
106 |
Die Size (mm²) |
106 |
66 |
+/-130 (112 for 1 MB L2) |
115 |
Maximum Clockspeed (MHz) |
1400 |
2700 (liquid cooled) |
3800 |
2600 |
Pipeline Stages ( fp) |
7 |
16 (21) |
31 - 39* |
12 (17) |
issue rate (Instruction per clockcycle) |
3 + 1 Branch |
4 + 1 branch |
4 ports, max. 6 (3 sustained) |
6 (3 sustained) |
Integer issue rate (IPC) |
3 + 1 Branch |
2 |
4 (3 sustained) |
3 |
Floating point issue rate (IPC) |
1 |
2 |
1 |
3 |
Vector issue rate (IPC) |
2-4 ( Altivec) |
2-4 ( Altivec, velocity) |
4 Single(SSE-2/3) |
4 Single(SSE-2/3) |
2 Double (SSE-2/3) |
2 Double (SSE-2/3) |
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Load & Store units |
1 |
2 |
2 |
2 |
"instructions in flight" (OOO Window) |
16 |
215 (100) |
126 |
72 |
Branch History Table size (entries) |
2048 |
16384 |
4096 |
16384 |
L1-cache (Instruction/Data) |
32 KB/32 KB |
64 KB/32 KB |
12k µops (+/- 8-16 KB)/16 KB |
64 KB/64KB |
L2-cache |
256 KB |
512 KB |
2048 KB |
1024 KB |
L3-cache |
2 MB DDR SRAM 64 bit at 1/4 th of core clock |
none |
None |
none |
Front Side Bus (MHz) |
166 |
1350 (675 DDR) |
800 (200 Quad) |
N/A |
Front Side Bus (GB/s) |
1.3 Half Duplex |
10,8 Full Duplex |
6.4 Half Duplex |
N/A |
Memory Bandwidth (GB/s) |
2.7 |
6.4 |
6.4 |
6.4 |
Core Voltage |
1.6V |
1,1V ? |
1.38V |
1.4V |
Power Dissipation |
30W at 1 GHz |
+/- 59 (Typical) -80 Watt (max) |
110 W (Typical) |
92,6W (Max) |
|
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November 20, 2009
November 19, 2009