We've spent a lot of time comparing Intel's Core architecture to NetBurst and AMD's K8; however, we've stayed away from quite possibly one of the most confusing comparisons: Core 2 Duo vs. Core Duo.
Unlike its desktop predecessor, Core 2 Duo comes from the same genealogy as the Core Duo. Despite the similarities in name and in architecture, there are some fairly major differences between the two CPUs, some of which won't become apparent until next year. The table below should help summarize the differences:
| Core Duo (Yonah) | Core 2 Duo (Merom) | |
Manufacturing Process |
65nm |
65nm |
Die Size |
90.3 mm^2 |
144.9 mm^2 |
Transistors |
151M |
291M |
Clock Speeds |
1.20GHz - 2.33GHz |
1.06GHz - 2.4GHz+ |
FSB Frequency |
533MHz - 667MHz |
533MHz - 800MHz |
L1 Cache Size |
32KB + 32KB |
32KB + 32KB |
L2 Cache Size |
2MB Shared |
2MB - 4MB Shared |
Pipeline Stages |
12 |
14 |
Decoders |
1 complex + 2 simple |
1 complex + 3 simple |
Maximum Decode Rate |
3 |
4+1 |
Reorder Buffer |
80 |
96 |
Issue Ports |
5 |
6 |
Scheduling |
Unified Reservation Station |
Unified Reservation Station |
Scheduler (# of Entries) |
24 |
32 |
FP Units |
FMUL/FADD: 1 |
FMUL: 1 |
SSE Units |
1 |
3 |
Integer Units |
ALU: 2 AGU: 2 |
ALU: 3 AGU: 2 |
Load/Store Units |
Load: 1 Store: 1 |
Load: 1 Store: 1 |
Socket Interface |
Socket-M (PGA/BGA) |
Socket-M (PGA/BGA) & Socket-P (PGA/BGA) |
Compared to the desktop Core 2 Duo (Conroe), the mobile version is architecturally no different. Obviously clock speeds (both CPU and FSB) are lower because these things will be going in notebooks where power consumption is more of a concern, but other than that the architectures are identical.
Compared to Yonah, Merom has some very clear advantages; on the surface the larger L2 cache is responsible for the 140M increase in transistor count, but architecturally the improvements extend far beyond that. You can get the details from the table above or from our previous articles on Intel's Core 2 processors, but simply put Merom is wider and slightly deeper than Yonah. The slightly deeper pipeline helps increase clock speeds on Merom (which will bump performance a bit), but the added decode and execution width will increase overall performance.
Not listed in the table above are the improvements to the cache subsystem and memory accesses on Core 2 Duo. Merom features more aggressive prefetchers than Yonah, as well as Intel's Memory Disambiguation technology that allows for out of order loads. In other words, not only is Merom able to operate on more data at once, at a faster speed, but it can also get access to that data quicker.
The first versions of Core 2 Duo are completely backwards compatible with the Napa platform that Core Duo currently uses, and thus they share the same Socket-M interface. Unfortunately for Merom, Napa only supports a maximum of a 667MHz FSB and thus has almost 40% less bandwidth to the CPU than the desktop version, and is identical to what the fastest Yonah CPUs use. The problem with FSB limiting Merom like this is that Merom is a hungrier core (as we've seen by the table above) than Yonah, so it needs a faster FSB in order to truly stretch its legs. The tradeoff is that a faster FSB consumes more power, thus reducing battery life, not to mention that you'll need a "new" chipset to support the faster FSB.
That new chipset is part of Intel's Santa Rosa platform, to be introduced in early 2007. Santa Rosa is composed of Intel's upcoming Mobile 965 chipset, ICH8M and a new wireless solution with 802.11n support. The new chipset will add official 800MHz FSB support, and thus Core 2 Duo processors released next year will be able to use the faster FSB. The Santa Rosa platform also introduces a new pin-out, Socket-P, for Core 2 Duo processors. Unfortunately that means you won't be able to use current Core 2 Duo and Core Duo processors in Santa Rosa based motherboards and notebooks.
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