Besides all the talk about the future architecture, there's not much to say about the desktop parts. Here's the current roadmap.

Intel Desktop Performance Roadmap
Processor Core Name Clock Speed Socket Launch Date
Pentium 673 Cedar Mill 3.8 2MB LGA 775 2H'06
Pentium 672 Prescott 2M + VT 3.8 2MB LGA 775 Q4'05
Pentium 663 Cedar Mill 3.6 2MB LGA 775 Q1'06
Pentium 662 Prescott 2M + VT 3.6 2MB LGA 775 Q4'05
Pentium 653 Cedar Mill 3.4 2MB LGA 775 Q1'06
Pentium 643 Cedar Mill 3.2 2MB LGA 775 Q1'06
Pentium >= 633 Cedar Mill 3.0 2MB LGA 775 Q2'06
Pentium 631 Cedar Mill (no VT) 3.0 2MB LGA 775 Q1'06
Pentium 571 Prescott 3.8 1MB LGA 775 Now
Pentium 561 Prescott 3.6 1MB LGA 775 Now
Pentium 551 Prescott 3.4 1MB LGA 775 Now
Pentium 541 Prescott 3.2 1MB LGA 775 Now
Pentium 531 Prescott 3.0 1MB LGA 775 Now
Pentium 521 Prescott 2.8 1MB LGA 775 Now

The single core Pentiums remain unchanged from last month, with the exception of the 673 showing up at the top. Processor models ending with a 3 will use the new Cedar Mill core, the single core version of Presler. They will be based on 65nm process technology and will include all the same extra technologies we mentioned earlier. They will also have HyperThreading enabled, where the dual core Presler chips do not. There is also a potential lower end 633 model scheduled to be introduced in Q2'06, though it may or may not be released, likely depending on demand and yields.

One final update for the mainstream desktop market is that the EM64T enabled 5x1 Pentium chips are finally available. We've been talking about them for a few months, and retail availability was expected before now. They were probably held back to let inventory of the earlier versions clear out. You can see the new chips in our Pricing Engine.

Intel Desktop Value Roadmap
Processor Core Name Clock Speed Socket Launch Date
Celeron D ??? Cedar Mill 512K + EM64T ??? LGA 775 2H'06
Celeron D 355 Prescott 256K + EM64T 3.33 256K LGA 775 Q4'05
Celeron D 351 Prescott 256K + EM64T 3.2 256K LGA 775 Now
Celeron D 346 Prescott 256K + EM64T 3.06 256K LGA 775 Now/Soon
Celeron D 341 Prescott 256K + EM64T 2.93 256K LGA 775 Now/Soon
Celeron D 336 Prescott 256K + EM64T 2.8 256K LGA 775 Now/Soon
Celeron D 331 Prescott 256K + EM64T 2.66 256K LGA 775 Now/Soon
Celeron D 326 Prescott 256K + EM64T 2.53 256K LGA 775 Now/Soon

The Celeron picture is similar to the single core Pentium market. The EM64T enabled Celeron D chips are all starting to ship, after a month or two of waiting. Once again, you can check the current prices and availability on our Pricing Engine - at present the 351 is available, but we aren't picking up any of the slower "+1" parts. Current generation Celerons do not have VT, HT, or EIST support, but they do include XD (as have all Celeron D chips since the "J" variants started shipping almost a year ago).

Once Intel transitions to 65nm, a new version of the Celeron based off the Cedar Mill core will arrive. Clock speeds are not yet set, but we do know that it will continue to use a 533 MHz FSB, and it will increase the amount of L2 cache to 512K. That will make the chip relatively interesting, as the old Northwood core also included 512K of cache. Of course, the pipeline of Northwood was only 20 stages rather than 31, so clock for clock Northwood may still be faster. With a 65nm process, however, we expect the chips to be able to hit relatively high clock speeds, and architectural tweaks may help them to surpass Northwood performance. You're still looking at relatively equivalent performance for around $100 a CPU, which compares favorably to the higher end Northwood cores of the past.

If you're in the market for a value system and you feel the need to purchase a 64-bit processor, we'd recommend that Intel buyers get a motherboard that uses the 945P or 945G chipsets. If you don't feel the support for dual core processors is important, we'd still recommend 915G/P as being the next best alternative. We would stay away from the 915GV/GL/PL chipsets as they have limitations that make them unattractive; not to mention the fact that those chipsets are almost EOL by now too. 915GV is like 915G, but no external graphics port is provided. 915GL has the same problem, but it only supports DDR memory instead of DDR or DDR2. Finally, 915PL supports an external X16 PCIe slot but eliminates DDR2 support and allows the use of 1 DIMM per memory channel, limiting you to a maximum of 2GB RAM. The bottom line is that the P or the G versions are what most mainstream users will desire. There's also the 955X chipset on the high end, which allows the use of up to 8GB of RAM. Those who really need the increased address space of a 64-bit OS will likely want the option to use more than 4GB of RAM as well.

Final Thoughts

Most of the major releases of 2005 have now occurred, and other than a speed bump or two, there's not much else awaiting Intel owners (at least in the desktop market) this year. 2006 has quite a bit more in store. We haven't covered the mobile section, but many expect to see the dual core Pentium M Yonah available for the desktop as well as mobile markets. Beyond that, we're all waiting for Intel's answer to the performance conundrums of the past year, where they officially lost the performance crown to AMD and haven't been able to regain it. The change to 65nm processes will likely have some advantages, but the real counterattack is going to come in the form of the next Intel architecture. We've given some speculation as to what may be present, but most of the real details are still closely guarded secrets.

For nearly 25 years Intel was the leader in PC processor technology and performance, and we have a suspicion that they will be pulling out all the stops to regain that lead in 2006. The fact that they still lead in profits and market share gives them a lot of resources they can apply to that goal, and we eagerly await additional details of the new architectures. AMD will naturally have their own new processors and architectures, but we know even less about K9 than we do about Conroe. Waiting is the hardest part, unfortunately.

Thinking About Conroe
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  • IntelUser2000 - Monday, August 22, 2005 - link

    First Itanium is 6-wide
    Itanium 2 is 6-wide

    Itanium 2 doesn't increase the issue rate, what Itanium 2 does is increase the possibility that IPC of 6 is possible by making better architecture.

    Brief overview of Itanium architecture: The CPU processes the EPIC instructions by using two bundles of 3 instructions each, therefore achieving IPC of 6. Each bundle can have a certain combination of different instructions.

    Main execution units in Itanium consists of 4 different kinds, that is Branch unit, Floating Point Unit, Memory Unit, Integer Unit. Memory and Integer unit can be considered in simple terms as ALU from what I understand.

    In one bundle, you can have certain combinations of those execution units. Examples may be: MMI(memory, memory, integer), MII, MIF, BBB, and such. Remember that each bundle can have that combinations, and there is like 26 combinations or so. That means if the second bundle can't have that combinations due to the lack of execution units, 6-wide isn't possible.

    Itanium had 2 M units, 2 I units, 2 FP units, 3 B units. So if the first bundle is MMI and the second bundle is MMI, it can't have 6-wide execution.

    According to the article I read, first Itanium can have in theory of ~3.8 IPC due to lack of execution units, and Itanium 2 have theoretical IPC of 5.6-5.7 due to more execution units, specifically 4 M units rather than 2 as in Itanium.


    There are two kind of ways to run 32-bit for Itanium. One way is the hardware emulator that's in all current Itanium chips. The 32-bit performance for first Itanium runs 32-bit x86 code as worse as 66MHz 486, or good as 200MHz Pentium MMX, when Itanium is running at 800MHz. Itanium 2 has better hardware 32-bit emulator plus better overall Itanium architecture, so 32-bit performance increases to around equal to 300MHz Pentium II(1GHz Itanium 2 has twice the performance or better compared to 800MHz Itanium in native code). That's pretty bad, makes running 32-bit practically useless, and according to the review, the compatibility was not so good either, as Quake 3 wouldn't install(not that running Quake 3 on Pentium 100MHz equivalent isn't sort of a push). Plus it takes additional die space and power consumption, which is not that much but a lot for a almost useless feature.

    So Intel introduced a dynamic software translator for the Itanium called IA-32EL(Execution Layer). By translating x86 instructions to EPIC instructions and optimizing them on run-time, performance improved dramatically while, taking out the need to have hardware emulator. 1.5GHz Itanium 2 with 6MB L3 cache is now equal to equivalently clocked Xeon MP(with hardware it would have been equal to 450MHz Pentium II) or better, which isn't that bad, and much better than the hardware one.

    Montecito seems to not have the hardware emulator anymore.
  • JarredWalton - Tuesday, August 23, 2005 - link

    Dang, I *swear* I read an article on HP.com or Intel.com stating Itanium 2 was 8-wide. I can't find it anymore, but there are many saying 6-wide. Weird. Anyway, I've read plenty about the rest of the Itanium architecture, and I don't know why you're suddenly going off about it. I'll correct the issue width statement, though.

    Not like it matters now, as we all know Conroe is 4-wide now. (I really expected that to be the case, but was told to make it less certain and more speculative for the article.)
  • IntelUser2000 - Thursday, August 25, 2005 - link

    http://www.intel.com/design/itanium2/datashts/2509...">http://www.intel.com/design/itanium2/datashts/2509...

    The intro shows that its 6-wide, 8-stage pipeline deep architecture. 8 does stand for something but I forgot what. I babbled on because it wasn't directed all at you, but I hoped somebody who didn't know and want to know may look at it.
  • JarredWalton - Friday, August 26, 2005 - link

    Argh! WTF is going on? Am I senile? I'm positive I read something about Itanium 2 (McKinley, etc.) being more than 8 pipeline stages. It stated something about the 8 stages of Merced being part of the reason Itanium 1 never reached higher clock speeds. Damn... people must just make stuff up about these architectures. :|
  • IntelUser2000 - Thursday, September 1, 2005 - link

    quote:

    Argh! WTF is going on? Am I senile? I'm positive I read something about Itanium 2 (McKinley, etc.) being more than 8 pipeline stages. It stated something about the 8 stages of Merced being part of the reason Itanium 1 never reached higher clock speeds. Damn... people must just make stuff up about these architectures. :|


    Itanium "Merced" is 10 stage pipelines. Nearly everyone that looked at the architecture said it was a bloated design, that was released in haste. By improving design tremendously over Itanium, Itanium 2 Mckinley reduces that to 8 stage pipeline while clocking 25% higher at the SAME process.

    Itanium-800MHz, 0.18 micron, 10 stage pipeline, 9 stage branch miss stages
    Itanium 2-1GHz, 0.18 micron, 8 stage pipeline, 7 stage branch miss stages
  • nserra - Friday, August 19, 2005 - link

    I agree IntelUser2000, but even so, if each core used c&q with some disable core capability, would be in the 30W per core range (120W total) right on track with prescott 2M and Pentium D.

    I don’t know if you noticed, but amd added more power to their designs while their processor are consuming less.... that must be because:

    Good reasons first:
    -amd will achieve higher clock speeds 3.4 GHz and up
    -amd is already thinking in 4 cores processors

    Bad reasons:
    -amd will come with some bad 65nm tech
    -or will come with some bad core (M2 with rev.F prescott like)
  • dwalton - Monday, August 15, 2005 - link


    "Intel Q3'05 Roadmap: Conroe Appears, Speculation Ensues"

    I almost spit my coffee onto the keyboard when i read that title. Came off to me as Intel released a roadmap showing the Conroe release in the third quarter of this year.
  • JarredWalton - Monday, August 15, 2005 - link

    Sorry to disappoint. :p

    Intel's lead time on the roadmap is about 18 months, though the initial details are often lacking. With Conroe/Merom being a new architecture, I doubt Intel will do so much as mention a clock speed without NDAs.
  • IntelUser2000 - Friday, August 12, 2005 - link

    Intel's 45nm is supposed to signal high-K, metal gates, and possibly tri-gate transistor structure. By using tri-gate, its supposed to be fully depleted substrate from the start. So, if they implement what they say they will according to their presentations:

    -High-K
    -Metal
    -Tri-gate, which brings FD-SOI

    We should see Yonah before worrying about Conroe. The specs of Yonah is pretty interesting.
  • JarredWalton - Saturday, August 13, 2005 - link

    Yonah looks interesting in some ways, but as far as I can tell it's just Dothan on 65nm with dual cores, improved uops-fusion, and hopefully better FP/SIMD support. I haven't even heard anything to indicate it will have 64-bit extensions, which makes it less than Conroe in my book. Not that 64-bit is the be-all, end-all, but I'm pretty sure I've bought my last 32-bit CPU now. I'd hate to get stuck upgrading for Longhorn just because I didn't bother with a 64-bit enabled processor. Bleh... Longhorn and 64-bit is really just hype anyway, but we'll be forced that way like it or not. Hehehe.

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