AnandTech: Understanding the Cell Microprocessor

Cell’s In-Order Architecture

We have mentioned that both the PPE and SPEs are in-order cores, but in order to understand the impact of an in-order core on performance, there’s a bit of background knowledge that we have to go over first.

Dependencies, Instruction Ordering and Parallelism

What are Dependencies?

In many of our past CPU articles, we’ve brought up this idea of dependencies as seen by the CPU. At the very basic level, a CPU is fed a stream of instructions that are generally of the form:

OP destination, source1, source2, ... , source n

The instruction format will vary from one CPU ISA to the next, but the general idea is that the CPU is sent an operation (OP), a destination to store the result of the operation, and one or more sources on which to get data to perform the operation. Depending on the architecture, the destination and sources can be memory locations or registers. For the sake of simplicity, let’s just assume that for now, all destinations and sources are registers.

Let’s take a look at an example with some data filled in:

ADD R10, R1, R2

The above line of assembly would be sent to the CPU, telling it to add the values stored in R1 (Register #1) and R2 and store the result in R10. Simple enough. Now, let’s give the CPU another operation to crunch on:

MUL R11, R10, R3

This time, we’re multiplying the values stored in R10 and R3, and storing the result in R11. As a single line of assembly, the above code is easily executed, but when placed directly after our first example, we’ve created a bit of a problem:

ADD R10, R1, R2
MUL R11, R10, R3
ADD R9, R11, R4

Line 1 writes to R10, while Line 2 reads from R10. Under no circumstances can the CPU begin executing line 2 before line 1 completes - the same goes for lines 3 and 2. What we’ve created here is what is known as a RAW dependency, Read After Write. There are many more types of dependencies, but understanding this basic example is more than enough to take us to the next topic at hand - the impact of such dependencies.

The problem with a dependency is that it limits what can be executed in parallel. Take the Athlon 64, for example. It has three integer execution units, all of which are equally capable of executing the code (in a slightly revised, x86 assembly format, of course) that we used above. In theory, the Athlon 64 could execute three lines integer operations in parallel at the same time - assuming that no dependencies existed between the operations. In executing the above code, two of the Athlon 64’s integer execution units would go idle until the first line of code was executed.

Dependencies, such as the simple one that we talked about above, hinder the ability of modern day microprocessors to function to the best of their abilities. It’s like having three hands, but only being able to clean your room by picking up one item at a time; frustratingly inefficient.

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