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  • ratbert1 - Saturday, June 21, 2014 - link

    When using acronyms it is common to expand it on the first usage. I find it amusing that TCO and ASICs are expanded, but field programmable gate array (FPGA) is nowhere in the article. I had no idea what it was. Not just you Rahul. This happens a lot on this site. Reply
  • blowfish - Saturday, June 21, 2014 - link

    Very well said, ratbert1, +1 on that! Reply
  • Stochastic - Saturday, June 21, 2014 - link

    I feel that Anandtech writers (not Anand so much--he's better about this) often assume that their readers have a lot of background knowledge. As someone who didn't major in engineering or computer science in college, a lot of this stuff is new to me. Of course with Google and Wikipedia it doesn't take long to educate myself, but it becomes tedious to do this with almost every article I read. Anandtech is special in that it's not afraid to get into the gory details that more mainstream tech sites ignore, but this often comes at the cost of accessibility. Reply
  • dac7nco - Sunday, June 22, 2014 - link

    You should try reading David Kanter @ Real World Technologies. Eeesh. Reply
  • bobbyh - Sunday, June 22, 2014 - link

    Being an engineering student I feel like they do not go into as much detail as i remember. That could have just been when I knew less though. Reply
  • ZeDestructor - Sunday, June 22, 2014 - link

    I dunno...

    I've been pretty happy with RWT's coverage and depth. Kanter does however seem to assume that you can implement most of the blocks in use there, as well as apply the more basic/common optimization techniques in use. Thus he focuses more on how everything plugs together to make things faster and reduce power usage.
    Reply
  • nofumble62 - Sunday, June 22, 2014 - link

    You can try to down load the Microsoft paper and read by yourself. Reply
  • ivanc - Tuesday, June 24, 2014 - link

    I couldn't agree more.
    Please go to a less technical site if you need more background, or do your own research.

    I do not want to see AnandTech become more like Ars Technica.
    Reply
  • modododo - Saturday, June 21, 2014 - link

    What's MS, ISCA, PCIe, GB, Gb, SAS, CPU, GPU, DDR, RAM, CL in OpenCL and ESL in AutoESL? Reply
  • GiantPandaMan - Saturday, June 21, 2014 - link

    Given that this is the web, it would be nice if the site had a mouseover definition system in place for desktop users.

    It never ceases to amaze me that even the most technical sites don't use the power of the web to make reading and understanding things easier. Tech timelines with links to articles. Mouseover glossaries. Button in a corner somewhere to play the latest podcasts while reading. etc.
    Reply
  • nevertell - Saturday, June 21, 2014 - link

    The day anandtech has mouse-over popups in their articles is the day tech/computer journalism will be dead. Reply
  • tuxRoller - Saturday, June 21, 2014 - link

    These aren't ads, and properly created popovers will disappear on mouse leave the area. Or you could use js to force clicks to get the same effect (and it'll be mobile friendly).
    These kinds of things can be done pretty easily with a good cms.
    Reply
  • Senti - Sunday, June 22, 2014 - link

    People are really lazy nowadays. It's not like you have to go to library now and spend several hours looking for such answers... Reply
  • nevertell - Sunday, June 22, 2014 - link

    The best they could do is just add a dictionary of the abbreviations and terms after every article that'd be linked to wikipedia or some other online resource. Popups are too disruptive. And in this day and age, if you can't be bothered to select a bit of text and use it to search for the selected text in a search engine of your choice to access the biggest vault of knowledge known to man, maybe you're not worthy of the knowledge you claim to be seeking. Reply
  • MrSpadge - Monday, June 23, 2014 - link

    Why force every reader into researching these things themselves when the author is an expert who could provide a short explanation right to the point that matters for the current article? Sure, it takes more time to write such additional information down, but it saves many others lot's of time and can probably often be reused. If this brief information is not enough everyone is obviously still encouraged to do their own search, adapted to their own interests.

    A mouse-over which disappears properly provides the information right where you need it - in contrast to a glossary, where you had to navigate to some other place to read, and then find the place again where you just left.
    Reply
  • Flunk - Sunday, June 22, 2014 - link

    Adding a automatic clickable explanation system for acronyms would be a good idea. It would save author's time and help out less knowledgeable readers. Wouldn't be hard to implement either. Reply
  • p1esk - Sunday, June 22, 2014 - link

    What is the point of expanding FPGA? If you don't know what it stands for, the expansion won't help you understand what it is. Even a short explanation won't do much good if you're not familiar with basic concepts of digital design.
    I think the best way to handle such abbreviations is to link to the appropriate articles on Wikipedia.
    Reply
  • potato32 - Saturday, June 21, 2014 - link

    Anyone want to hire an FPGA design engineer? Of course, I think that higher level code to gates translation would yield sub-optimal performance :) Reply
  • wintermute000 - Sunday, June 22, 2014 - link

    I'm no CS major nor do I design hardware but intuitively it seems like a properly implemented FPGA setup would of course beat out generic x86 for parallel tasks, the only question is the efficiency and logistics of porting/implementing such code (in a holistic sense e.g. include say cost and ease of hiring a bunch of verilog/OpenCL gurus vs generic programmers). Reply
  • ZeDestructor - Sunday, June 22, 2014 - link

    Not parallel, just endlessly repeatable. The most efficient core at times is a straight purely combinational single-op core. In practice though, people tend to go for a somewhat more modular design with a small number of ops available, simply to significantly simplify testing. Reply
  • Henriok - Saturday, June 21, 2014 - link

    IBM's PCI based CAPI interface that's built into the POWER8 will enable FPGAs and ASICs direct access ro the CPU and memory and Xilinx and Altera has already shown tremendous results in all kinds of areas. Reply
  • quanstro - Monday, June 23, 2014 - link

    the network is CL3 (SerialLite III) over SFF-8088 SAS cabling, NOT SAS. (see section 3.2 of the paper.) Reply
  • MrSpadge - Monday, June 23, 2014 - link

    It might be cool if Intel could connect coprocessors like FPGAs to their ring bus, just like they connected Crystalwell to one port. I wouldn't mind if the first FPGAs were multi-chip packages, as long as performance doesn't suffer too much but the price benefits from using regular CPU dies. Reply

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