Back to Article

  • kpb321 - Wednesday, January 29, 2014 - link

    From what I understand this is a bigger deal than it would seem. Unlike x86 where pretty much everyone builds cpus/chipset with a set baseline that is needed to boot windows ARM SOCs aren't as standardized and might have different types of buses available, might handle the boot sequence differently etc which is a difficulty for the OS and part of the reason why most ARM SOCs can't just compile and run the standard linux kernel.

    Interestingly, Microsoft did something similar for their Windows Phone and tablets to make things easier on them.
  • FwFred - Wednesday, January 29, 2014 - link

    Much needed move, good to see this is already implemented on the first AMD ARM soc.

    Unfortunately this underscores the challenge facing the ARM server ecosystem. x86 architecture just isn't the ISA.
  • Krysto - Thursday, January 30, 2014 - link

    Agreed. I hope this leaks into the mobile market, too, so we can finally have that standardized OS image for smartphones. I hope Android 5.0 allows for that, especially if it comes with kernel 3.8+, which I believe supports device-tree, which should make it easier to do this.

    I realize we probably still won't see Samsung OS images running on Sony hardware, but it would be nice if at the very least a Sony OS image would run on ALL Sony mobile hardware, or a Samsung OS image running on ALL Samsung mobile hardware, and so on. I really hope Google and their partners have been working on this already, and it's ready for Android 5.0. It would be by far the biggest announcement for Android this year (even if it will take a bit to see the results of that with new hardware).
  • Hrel - Wednesday, January 29, 2014 - link

    "As a result, the maximum number of CPUs in the system is 8"

    Isn't that gonna become a problem... really quickly?
  • bobbozzo - Wednesday, January 29, 2014 - link

    Hrel, That's the BASE system with the base interrupt controller. Reply
  • extide - Wednesday, January 29, 2014 - link

    Not really, many of these high density ARM setups (like moonshot, etc) consist of many small servers, so that limit would apply to each server, not the whole thing. Reply
  • Krysto - Thursday, January 30, 2014 - link

    No. If a CPU is an atom, think of the whole thing as a molecule. Things are built of many molecules, and so are server farms. They could've decided to make it 4-core only, but I guess they thought the whole system makes more sense with 8-cores. They can probably upgrade the spec in 2 years for 16-cores anyway, for 16nm-10nm processes. Reply
  • JohanAnandtech - Thursday, January 30, 2014 - link

    Exactly, this is the first spec. Reply
  • npz - Friday, January 31, 2014 - link

    The problem is that it prevents licensees like AMD in creating a multi-socket system or multi-processor on a die, say, using their own proprietary interconnect. It really limits this first version of the spec to pure micro-server duties, restricting scaling out only in the form of individual, separate but networked systems (small dense blades, etc). Reply
  • btb - Friday, January 31, 2014 - link

    If the primary intended use is lots and lots of small blades, perhaps it makes good sense? Just guessing here, but its probably simpler to nail down a design spec if they dont have to deal with multi-socket issues, interconnects etc. Reply
  • BMNify - Friday, January 31, 2014 - link

    if you assume that they are using existing generic ARM IP then the interconnect isnt really a big problem they have whats now called NOC (Network On Chip) the current The ARM® CoreLink™ CCN-508 Cache Coherent Network scaling up to 32 processor cores can deliver up to 1.6 terabits of sustained usable system bandwidth per second with a peak bandwidth of 2 terabits per second (256 igaBytes/s) at processor speeds, but its probable that AMD are using the older CCN-504 scaling to 16 processor cores and one Terabit of usable system bandwidth per second.

    OC if you actually look a little deeper into current and near term interconnects rather than relying on most high profile tech sites that don't seem to look to far beyond the usual PR suspects...

    ... then you find the "Si photonics" and packaging is to see Si photonics (at 40Gbit/s per interconnect link) commoditized as in easy to obtain on chip/package perhaps by 2016/17, the foundries and volume packagers are all ready now with 2.5D and even 3D ready to go apparently.

    Si Photonics: 3D ASIP’s Pre-game Show
    "At this week’s 3D Architectures for Semiconductor Integration and Packaging (3D ASIP) which took place Wednesday, December 11, 2013 at the Hyatt Regency San Francisco Airport, it became clear that High Bandwidth Memory (HBM) is more likely to be the application that brings 3D TSVs to volume manufacturing. However, according to Dim-Lee Kwong, executive director of IME in Singapore, Si Photonics holds the key for integration of memory and logic, and enables wafer level integration of multiple components. Individually, While Si photonics and through silicon interposers (TSI) each provide advantages over scaling and monolithic SoCs, Kwong says together they can move “Moore’s Mountain” as we approach CMOS scaling limits."
    “TSI provides a nice platform for interconnecting photonic ICs (PIC), logic, Memory and CMOS as close as possible on the interposer.” said Kwong.

    only the mass markets fabless providers only need to actually design
  • MrSpadge - Thursday, January 30, 2014 - link

    It's OK for the target market of many small servers. It wouldn't work for HPC, but there you'll typically want either GPUs (or similar designs) for embarrassingly parallel tasks or fewer fat cores and unified memory for other tasks due to limited scalability. I don't see much space for solutions in between these extremes.. which is not yet covered by x86.

    What I wonder, though, is if the whole concept of micro servers really makes sense from a load balancing point of view. If I'd put many more energy efficient cores into a big box and run many more VMs on them, wouldn't that be better than many small independent servers? It would still be quite energy-efficient, but the CPUs and memory can be shared among the entire system. Well, the high performance interconnects needed in this case must not consume too much power.. but I don't think this would be troublesome at 8 cores.
  • duploxxx - Friday, January 31, 2014 - link

    while this article mentions the standardization of server specs, that doesn't mean the arm cpu can't be used for anything else...

    HP moonshot is the example you refer too where virtualization is not needed (yet) but specific target markets are already addressed. other types and designs will probably follow soon. It market is changing quite a bit, default server layout will change more soon.
  • BMNify - Friday, January 31, 2014 - link

    thats true , OC the ‎Calxeda and moonshot 32bit ARM prototypes where fine as a proof of concept, but their first product layout of their but ugly SLED's use of the available space what nothing but shameful ,tons of useless metal and wasted space in a given U configuration restricting airflow etc...

    ‎Calxeda's NOC was apparently good but they should have sacked the SLED designers , using small self contained COM (computer On Modules) and providing a simple PCB plastic slide mount at minimal distance between PCB cards to direct airflow would have been far more rewarding and cst less to produce, as you could then re-purpose these separate COM when it became time to upgrade.... it's a shame really , lets hope someone in the server space learns that lesson and provides what people want to actually buy this time around.

    on a side not its funny that Microsoft have now also joined this ARM imitative :)
  • lwatcdr - Monday, February 10, 2014 - link

    I do not think so. This should really work well in the SAN and NAS space as well as web servers. Reply

Log in

Don't have an account? Sign up now