POST A COMMENT

39 Comments

Back to Article

  • anexanhume - Friday, September 20, 2013 - link

    That's a huge block of cache/SRAM above the GPU. Reply
  • tipoo - Friday, September 20, 2013 - link

    Looks like it. Built in framebuffer? If you look at the Wii Us GPU, there is something similar on it, a small 1MB SRAM pool, but that's thought to be for Wii backwards compatibility but may have some other interesting performance implications. Reply
  • A5 - Friday, September 20, 2013 - link

    Maybe a buffer for the ISP to handle burst mode/slow-motion? Reply
  • tipoo - Friday, September 20, 2013 - link

    In a teeny SRAM pool? Not a large chance. That thing is probably ~1MB. Reply
  • SiliconGeezer - Friday, September 20, 2013 - link

    The CPU cores look much denser than the A6 cores, together with the new SRAM cache, and the 32-28 shrink it might explain the doubling of transistors 'marketing comments'. This looks like quite a big design change. Congrats to the lab guys at Chipworks, I know these die photos are not easy to make. Reply
  • bartoni - Friday, September 20, 2013 - link

    Perhaps it is a 4MB L3 cache. That would explain some of the performance gain. Reply
  • stacey94 - Sunday, September 22, 2013 - link

    Isn't cache very power intensive? Reply
  • Samus - Tuesday, September 24, 2013 - link

    I don't know, look at Haswell: huge caches, 7-watt CPU's. Reply
  • Rec - Friday, September 20, 2013 - link

    Anand in the article you have mentioned Samsung 22nm, is that a typo ? Shouldn't it be 28nm ? Reply
  • Khato - Friday, September 20, 2013 - link

    Will certainly be interesting to see what Chipwork's annotated version looks like for the rest of the chip, but I'd be quite surprised if you aren't correct on the CPU and GPU cores.

    For the fun of it, unless I've made a mathematical error it looks like the 2x Cyclone cores + cache are around 17.76mm^2 while the 2x Swift cores + cache are only 15.82mm^2.
    Reply
  • bartoni - Friday, September 20, 2013 - link

    The A6 Swift cores were full-custom stack-based physical design, but these A7 Cyclone cores appear to be sea-of-gates with custom arrays like the rest of the SoC blocks. So the Cyclone cores may have much higher areal logic density than the Swift. Reply
  • MrSpadge - Saturday, September 21, 2013 - link

    Considering the performance massive increase at the same clock speed of Cyclone over Swift it's actually surprising the cores are not much larger. Could be the increased packaging density (in addition to the process shrink) which bartoni mentioned, though. Reply
  • Khato - Sunday, September 22, 2013 - link

    I'm still waiting for more information/analysis before agreeing with the conclusion that there was no change in clock speed between A6 and A7. As per Anand's review, all programs that he ran pointed to the CPU cores still running at 1.3 GHz, but there's still the possibility of the software being incorrect/not reporting burst frequencies or the like.

    To put it into perspective, the size of gains the A7 is showing over the A6 in geekbench are comparable to a 3GHz Core 2 Duo against a 3GHz Pentium 4. For that to happen at the same frequency, especially with only a year between the designs, is rather difficult to believe. Especially when the scores are basically in-line with what's typically seen for a refinement of a design if a ~30% increase in core clock is applied to the A7.
    Reply
  • strappe - Friday, September 20, 2013 - link

    The L1 instruction & data caches were doubled in size to 64KB in Cyclone. L1 caches are usually virtually addressed, so with the move to 64-bit virtual addresses the cache address tag RAM would more than double in size also. This could account for much of the increase in the die area devoted to the CPU. Reply
  • Wilco1 - Friday, September 20, 2013 - link

    I-cache is virtually addressed but always physically tagged (VIPT). This means the number of bits in the tag is small. Given Apple doesn't need more than 4GB of DRAM on their 64-bit CPU, they only need the usual 20 tag bits. Reply
  • A5 - Friday, September 20, 2013 - link

    So the cores are called "Cyclone" now? I liked Oscar better :-p Reply
  • tipoo - Friday, September 20, 2013 - link

    "Oscar is a CPU core inside M7, Cyclone is the name of the Swift replacement."
    From the 5S review.

    Incidentally, M7 doesn't exist as a separate chip according to ifixit, as Apple seemed to imply. Instead it's integrated in A7.
    Reply
  • jasonelmore - Friday, September 20, 2013 - link

    the m7 is a separate chip, it was just hidden under some padding.

    http://ifixit.org/5311/apples-mysterious-m7-proces...
    Reply
  • easp - Saturday, September 21, 2013 - link

    And, no surprise, it is a commodity MCU. Reply
  • solipsism - Saturday, September 21, 2013 - link

    How do you get "commodity" out of the link supplied? Reply
  • stacey94 - Saturday, September 21, 2013 - link

    Because it says that it's an NXP LPC1800.

    Apple got it off the shelf from these guys and labeled it the M7:

    http://www.nxp.com/products/microcontrollers/corte...
    Reply
  • bhd2 - Monday, September 23, 2013 - link

    Hi,

    We (at Chipworks) did some poking around on the NXP website, looking at their LPC range of products; and we couldn't find any specific part that matched the look of the LPC18A1, particularly the 30-ball WLCSP packaging. So we've come to the tentative conclusion that this is likely a customised LPC18xx chip built for Apple, similar to those we've seen from Dialog and Cirrus over the years (A1 stands for Apple-1?).

    Could be M3, could be M0 (though the latter don't have the LPC18 prefix).
    Reply
  • toyotabedzrock - Tuesday, September 24, 2013 - link

    If it was truly custom it would have been printed with an apple logo. They just ordered a specific package. Reply
  • dylan522p - Saturday, September 21, 2013 - link

    When the review was originally posted Anand had not completely figured it all out yet and said that Oscar was the CPU and had no mention of Cyclone. He later fixed it. Reply
  • name99 - Friday, September 20, 2013 - link

    What's with the obviously differently colored parts that look higher res?
    We see a block of six of them in the middle of the chip, a seventh one in the CPU part, and two smaller versions also in the CPU part.
    Are those real or some image processing artifact of Chipworks and/or Anand trying to modify those parts of the image for higher contrast and sharpness?
    Reply
  • Tom Womack - Saturday, September 21, 2013 - link

    I think they're probably clock generators (PLLs) Reply
  • bhd2 - Saturday, September 21, 2013 - link

    They are not a processing artefact, it would be really difficult to select those areas for special treatment - it appears to be the effect of different device density. At this points I think PLLs is a good guess; if you look at the A6 image there are similar blocks in the top-left quadrant. Reply
  • bartoni - Saturday, September 21, 2013 - link

    Yes, the six small identical square blocks in the middle and the one square between the cores are very likely PLLs. Reply
  • tipoo - Saturday, September 21, 2013 - link

    It's because of different layouts and densities. It's the same reason you get different colors within the same decapped chip. Reply
  • HisDivineOrder - Saturday, September 21, 2013 - link

    Can't wait to see the iPad based on this SOC. Reply
  • rtnmbr - Saturday, September 21, 2013 - link

    Something inside me really wishes they'd go bonkers with a quad-core cyclone design. albeit highly unlikely, that would cause some major uproar in the industry. Reply
  • tipoo - Saturday, September 21, 2013 - link

    Yeah, this is a hugely efficient core for todays ARM standards, I'd kind of like to see it in a higher than iPad TDP quad core form to see what it could really do, at say, a sustained 2 GHz. Reply
  • bartoni - Sunday, September 22, 2013 - link

    Keeping more than two core's caches coherent is difficult. Going above 4 cores adds another layer of problems. It takes less design effort to reach higher performance with 2 cores than with more cores, but at some point simply improving the two core system is performance inefficient compared with a many-core system. The Intel Core and Atom lines followed that path. Perhaps Apple hadn't reached that point yet. However, a four Cyclone core SoC could be a competitive laptop processor giving Apple an option, and thus pricing leverage with Intel, for their MacBooks. Reply
  • nunomoreira10 - Monday, September 23, 2013 - link

    it´s just a matter of time before they put-it on the air, probably for the next high resolution update, imagine how much more money would apple make if intel was outh of the picture.
    make the air a facebbok machine and the pro 13 thinner to fill the niche
    Reply
  • Aenean144 - Sunday, September 22, 2013 - link

    And put it in a smartphone or a tablet?

    I think Apple is certainly thinking of iOS versions of Final Cut Pro, Logic Pro, Aperture and shipping say a 13" iPad with 128 GB storage and a quad-core Cyclone, and maybe a 2x 6630, but this a pretty niche device. One thing for sure, an A7X with 2-core Cyclone, a PowerVR 6630, and 2 GB RAM will finally be enough make 2048x1536 res iPads sing.
    Reply
  • Doomtomb - Saturday, September 21, 2013 - link

    I work at where these are being made :) Reply
  • name99 - Saturday, September 21, 2013 - link

    And you never told us about them! Shame on you!
    I vote you be expelled from the AnandTech community :-)
    Reply
  • toyotabedzrock - Tuesday, September 24, 2013 - link

    Is that a block of memory right next to the gpu? Reply
  • TeamToad - Thursday, October 03, 2013 - link

    Is there any update on when the annotated version of this will be done? I'm always really interested to read your in-depth analysis of the latest SoCs. Reply

Log in

Don't have an account? Sign up now