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  • sheh - Wednesday, August 21, 2013 - link

    Let me get this straight. So in summary, 2003 saw the introduction of cheese to flash cells? Reply
  • lecaf - Wednesday, August 21, 2013 - link

    I agree, while the video is well produced, the powerpoints are awful. Reply
  • GonzaloMin - Wednesday, August 21, 2013 - link

    Love my job, since I've been bringing in $82h… I sit at home, music playing while I work in front of my new iMac that I got now that I'm making it online. (Home more information)
    http://goo.gl/iGyZy6
    Reply
  • Streetwind - Wednesday, August 21, 2013 - link

    Great to see that someone found a way out of the dead end road that Flash development is driving down! Not sure if power consumption will really be that good though, considering we're talking about 30nm structures.

    Would be nice if you could do a companion piece looking at Crossbar's technology :)
    Reply
  • Kristian Vättö - Wednesday, August 21, 2013 - link

    According to Samsung, power consumption is up to 45% lower, see this slide:

    https://dl.dropboxusercontent.com/u/128928769/3D%2...

    Of course, until we get a sample of the new V-NAND SSD, we can't confirm that but I don't think it's far from the truth.
    Reply
  • MrSpadge - Saturday, August 24, 2013 - link

    With flash / NAND power consumption increases for smaller process nodes, not the normal way around. Reply
  • iwodo - Wednesday, August 21, 2013 - link

    Um, I am not sure i need those 10x endurance, even 2x will do fine. So with even more layers, move to TLC, and move to smaller node, we could see even higher then 1Tb? 10Tb perhaps?

    I wonder how much does it cost to convert old 30nm fabs to be able to produce V-NAND.

    I think with V-NAND we are definitely seeing the end of HDD, at least in consumer devices Something I thought wasn't coming that soon. HDD will properly continue to live on Servers and NAS. Where Huge capacity is needed.
    Reply
  • MrSpadge - Saturday, August 24, 2013 - link

    Yeah, they can scale to TLC and lower endurance at smaller process nodes just fine. Reply
  • Sjors E - Wednesday, August 21, 2013 - link

    Any change of an article like this on ReRam? I can't find a good
    "how it works" article on the internet, so I was hoping you could help me out here :)
    Reply
  • Sabresiberian - Wednesday, August 21, 2013 - link

    Yah it would be very nice to read an Anand treatment of the RRAM (ReRAM) concept. :) Reply
  • Jambe - Wednesday, September 04, 2013 - link

    Me three. Reply
  • Jaybus - Wednesday, August 21, 2013 - link

    It works completely differently than flash. In Crossbar's case, amorphous Si is sandwiched between a metallic top electrode (Ag) and a polysilicon bottom electrode formed in a crossbar structure. Rather than trapping electrons, whole atoms are moved around to chemically change the resistance between top and bottom electrodes of each individual cell. Each cell is a sort of variable resistor where current in one direction increases its resistance, while current in the other direction decreases its resistance. This is also known as a "memristor" because it remembers its current resistance state with or without current flow. There is a good intro article in EE Times at http://www.eetimes.com/document.asp?doc_id=1319139... describing Crossbar's technology. The article's comments go into more detail, but be forewarned the comments are written by EEs and are not for the faint of heart. Reply
  • Sjors E - Thursday, August 22, 2013 - link

    Thnx Jaybus, just the kind of article I was looking for! Reply
  • Kevin G - Wednesday, August 21, 2013 - link

    With 30 nm class V-NAND coming in at the same capacities as a hypothetical 15 nm die, things are looking good for continued storage growth. Not only will V-NAND have several major process revisions to further increase density, there is also the option to increase the number of vertical layers. 1 Tbit dies really do seem feasible by 2017. Reply
  • MartinT - Wednesday, August 21, 2013 - link

    24 layers of V-NAND sounds rather expensive to produce, never mind the 128 layers needed for the projected Tb device.

    If this is the solution, we're screwed.
    Reply
  • Solid State Brain - Wednesday, August 21, 2013 - link

    According to one of the slides above, with 8 layers needed for 16 Gb, but only 24 for 128 Gb it looks like benefits in capacity by adding more layers have an exponential trend. I can't quite figure out the exact relationship, but for 1 Tb V-NAND chips I guess that somewhere around 32 layers or so will be needed. Reply
  • SunLord - Wednesday, August 21, 2013 - link

    It really depends on how much a 24 layer 39nm wafer costs compared to a normal 19nm or smaller nand. Shrinking down to 15 nm or below is gonna get expensive with very low endurance. I kinda doubt Samsung would move forward into full scale production with something that will be more expensive to produce than what their rivals can make. I doubt Samsung will build a 39nm 1Tb V-NAND but if they due they'll probably before enterprise customers and we won't see them in consumer grade devices till they do a shrink down to 29nm.

    I have to say it's interesting that samsung labels there process in 10 nm classes such as 39-30nm and 29-20nm instead of just saying the exact size such as 34nm or 25nm like others due.
    Reply
  • jjj - Thursday, August 22, 2013 - link

    I highly doubt this chip is 24 layers , Samsung's language in the announcement was "can stack as many as 24 cell layers" and at 24 layers the density would be terrible compared to 2D , I was expecting 5-6 layers at best for this first chip. Reply
  • jjj - Wednesday, August 21, 2013 - link

    "Samsung introduced a first generation 128Gbit MLC V-NAND solution with 24 layers."
    Are you sure sure this chip is 24 layers? The press rls was saying up to 24 layers i believe so was expecting a lot less layers.

    Maybe worth mentioning that Micron is starting 16nm production and yields might be better on 2D NAND so not sure how cost effective 3D is now.
    As for the other big players they do have 3D NAND on their public roadmaps, most should go there in 2015-2016 , the timing is mostly about cost ( you can check their investors presentations or ask directly) but maybe Samsung is forcing them to accelerate their plans. Next seems to be 3D ReRAM by the end of the decade.
    Reply
  • James5mith - Wednesday, August 21, 2013 - link

    OK, I'm going to say something that might be really dumb here, but bear with me....

    "Defects in the transistor (e.g. from repeated writes) can cause a short between the gate and channel, depleting any stored charge in the gate. If the gate is no longer able to reliably store a charge, then the cell is bad and can no longer be written to."

    So why not mark that a permanent "0" bit, and use it as appropriate? I.e. Only write to that cell when it would contain a zero anyway. You are at a known state, so leave it drained, but it can still be useful to store bits in, as long as they are 0 bits. I understand that tracking this kind of thing might take some work, but it would be a way to get useful life out of a cell, even after it had died.
    Reply
  • Joel Kleppinger - Wednesday, August 21, 2013 - link

    Then you have to have another bit to store the value of that bit... and what's the point? Reply
  • Fujikoma - Wednesday, August 21, 2013 - link

    You'd use more addressing bits to point to that bit or you'd wear the SSD faster by analyzing it to overlay the data to match up with that bit. Reply
  • chaos215bar2 - Wednesday, August 21, 2013 - link

    What you're proposing amounts to not marking a block as bad immediately if a write fails, hoping that a future write will succeed anyway (possibly because it writes zeros to all the bad cells). I could easily imagine some controllers doing this already at the cost of a little performance, but once you have a few bad cells in a block, the chances of finding data that can actually be written to the block quickly get so low it doesn't seem worth trying.

    An alternative scheme would be to use error correction that could detect and correct some number of bad bits (say, n) and to allow writes up until the block has a smaller number of bad bits (maybe n/2). That actually seems like a better idea, assuming you can make n large enough.
    Reply
  • Azurael - Wednesday, August 21, 2013 - link

    Erm... Samsung eMMC... Every time they fix a previous fatal bug, they introduce a new one...
    http://wiki.cyanogenmod.org/w/EMMC_Bugs

    I'm assuming the NAND itself is probably okay and they've just got no clue how to make a working controller, but personally I avoid anything I know to contain Sammy flash...
    Reply
  • p1esk - Wednesday, August 21, 2013 - link

    It would be interesting to know how they implemented interconnect wires between all those layers. More wires to drive = higher current needed = more power dissipation. Also, more wires = more capacitance = higher delays = lower read/write performance.

    Chanel wrapping charge trap/gate is a good move, similar to FinFET idea.
    Reply
  • garadante - Wednesday, August 21, 2013 - link

    Hmm... Does anyone know if this V-NAND stacking is stacking individual wafers atop each other with vertical interconnects running down, or are they somehow managing to fab it like this? I'm assuming it's the first, where they're stacking individual wafers. While that seems good and great... if that's the case, that doesn't really increase the number of chips you can get off a single wafer. Now you're using 24 chips instead of 1. Seems like that wouldn't drive costs down without massively increasing production? Someone correct me if I'm wrong, but if I'm right and this is wafer stacking, can someone please explain how it's cheaper? Wafer costs are pretty much everything. Reply
  • strappe - Wednesday, August 21, 2013 - link

    This is a single wafer. In a conventional planar chip, all the channels of the every transistor lie side-by-side just below the top surface of the silicon wafer. Next, gates are formed directly on top of the wafer. Finally, alternating layers of insulation and metal are deposited to connect the transistors together; the insulation allows the metal wires to cross without short-circuiting. (A complex device like a microprocessor will often have over a dozen metal layers.)

    Instead of new layers of metal, Samsung is laying down new transistors. NAND flash was a big breakthrough (over the older NOR flash) by series-connecting all the transistors in a long string so they didn't have to be connected by metal (think of a Christmas light string). Samsung has flipped the string to make each one vertical.

    From the drawings, the channels of each device in the string form one long continuous column. Distinct devices are created by insulating the other FET elements (gate and charge storage) in each layer from the one above and below (you can see this shown in the video).

    Since each layer is the same, they all use the same masks, but the overall throughput has to be a lot lower because each wafer has to be processed many more times (I'd guess a minimum of three deposition steps to form each layer). So wafer costs will be higher. Figuring out how to keep all those layers consistent and aligned precisely (so that those columns really are vertical) must have been an enormous challenge.
    Reply
  • garadante - Wednesday, August 21, 2013 - link

    So either way, costs are going to increase with this. Density increases, but output decreases. I wonder how long it will be before we this in mass market storage devices at lower prices than traditional NAND. Reply
  • pdjblum - Wednesday, August 21, 2013 - link

    I for one totally favor larger transistor size and much longer endurance. And I rather rely on robust physical properties than error checking and manipulation. I don't want to have to worry about my data in five years, or even ten. Go samsung! Quality over quantity any day for me. Reply
  • MxxCon - Wednesday, August 21, 2013 - link

    So what are the drawbacks of this technology?
    This article talks about all the great benefits it'll bring, but what are its disadvantages?
    Reply
  • DigitalFreak - Wednesday, August 21, 2013 - link

    So does this mean we'll soon have 2.5", full-height SSDs? :0) Reply
  • Asmodian - Wednesday, August 21, 2013 - link

    Each layer is very thin, this stacking does not affect the overall thickness of the chip, let alone the drive.

    All the layers are FABed on one wafer, they are not stacking silicone chips. A drop in yield of 95.83% would be... unacceptable.
    Reply
  • p1esk - Wednesday, August 21, 2013 - link

    How do you know they're not stacking multiple wafers? Reply
  • DigitalFreak - Wednesday, August 21, 2013 - link

    'twas a joke... Reply
  • LeftSide - Thursday, August 22, 2013 - link

    I wonder if the s5 will have one of these chips. 128gb in a phone sounds nice. Reply
  • meloz - Thursday, August 22, 2013 - link

    This is the first SSD news that has me excited in months. True game changer! I was beginning to get bored with meagre incremental improvements in density/cost, but now it looks like we will get a big boost, just have to wait another 24 months or so.

    Other players will also have to find a way to offer higher density/cost to stay relevant, so we consumers can only win. The future of solid state storage looks bright. I see a future when you can get a high performance 128GB SSD for less than $30.

    As an aside, I found some of the illustrations used in the articles rather cute. Love how they gave each electron a 'home'. Samsung must have hired some comic book illustrator.
    Reply
  • Impulses - Friday, August 23, 2013 - link

    I imagine 128GB drives will eventually become irrelevant or just budget parts with last gen controllers/flash... Just like you don't see a HDD as small as 160GB on anything but a netbook anymore. Not hating, just saying, 128GB is rather small. I'm running two 128GB Samsung 830s btw. Reply
  • geok1ng - Thursday, August 22, 2013 - link

    if half of samsung's claims are true they have a product perfect for corporate market and very suitable for consumers devices. i do not like the prospects for people with money invested on microns stocks. Reply
  • Impulses - Friday, August 23, 2013 - link

    You're assuming Intel/Micron are just sitting on their hands? Reply
  • arnavvdesai - Thursday, August 22, 2013 - link

    This is exciting news from the NAND performance but like Anand mentioned I would love to get a very good long forma article regarding memresistors and how much of an impact will they have on computing in general. If your RAM is your HDD wouldn't we get an exponentially large leap in performance akin to something we got while moving from HDD to SSD? Reply
  • I_M - Wednesday, January 01, 2014 - link

    So where are those 480GB and 960GB Samsung V-NAND SSD that are supposed to be manufactured from Aug 2013?
    Looks like complete vaporware as of 1/1/2014. - not even part numbers could be found on Samsung websites.
    Reply
  • MarcSP - Friday, March 28, 2014 - link

    Now we know the real meaning of that V: Vapor-NAND :-P Reply
  • MarcSP - Friday, March 28, 2014 - link

    And if we flip vertically that V, it looks very much like "A-NAND":
    OMG, it was just a joke from Samsung to mess with Anand Shimp and Anandtech.com!
    Reply

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