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  • magreen - Thursday, May 05, 2011 - link

    Yeah how many people were looking at the chip? Reply
  • Abix - Thursday, May 05, 2011 - link

    What chip? Reply
  • IvanAndreevich - Thursday, May 05, 2011 - link

    It seems the photographer got the focus point all wrong Reply
  • sprockkets - Thursday, May 05, 2011 - link

    Yeah. To photographer, F-Stops, look it up. Reply
  • swimomatic - Friday, May 06, 2011 - link

    Advertising is getting too good. Reply
  • SunSamurai - Tuesday, May 10, 2011 - link

    FStops? lol?

    His fstop was fine, point of focus not so much.
    Reply
  • Icabus - Thursday, May 05, 2011 - link

    Sorry, did you say something? I was distracted. Reply
  • jubbbird - Thursday, May 05, 2011 - link

    It's funny because it's true.

    Kudos to the photographer, though. Everything is so artfully positioned...
    Reply
  • KidneyBean - Thursday, May 05, 2011 - link

    That was the best chip I ever had. Reply
  • Stuka87 - Thursday, May 05, 2011 - link

    Hey it got our attention! Reply
  • umbrel - Thursday, May 05, 2011 - link

    to match DRAM latency?
    At that point we would not need DRAM at all, just the SSD.
    For that matter, how fast a DRAM must be to match L3 cache latency?
    Reply
  • cjl - Thursday, May 05, 2011 - link

    Much. SSDs have latency of around a hundred microseconds at best right now, while DRAM is under 100 nanoseconds. That's a factor of a thousand or so. L3 cache latency is another factor of 10 or so better than that - around 10 nanoseconds. You won't really reach L3-like latencies with anything that isn't directly on the chip, since at that level, signal travel time becomes fairly significant. Reply
  • JasonInofuentes - Thursday, May 05, 2011 - link

    Again, while we don't have confirmation that this is going on, remember that latency can be hidden with speed, or slowness, elsewhere. If the speed between the controller and the pseudo-SLC NAND is faster than the SATA interface (it likely is) then you will not noticethe latency of the pseudo-SLC. There might be a performance penalty in non-cache data that would otherwise reside in SDRAM (think allocation tables). Reply
  • FATCamaro - Thursday, May 05, 2011 - link

    Apple has been consistently leapfrogging their competition as opposed to the Apple of old which was always a bit of a follower.

    Z68 chipset
    This new nand
    the small ssd's in the MBA
    iphone original and on and on.
    Reply
  • DigitalFreak - Thursday, May 05, 2011 - link

    Point, other than being a fanboi? Reply
  • JasonInofuentes - Thursday, May 05, 2011 - link

    Bear in mind that Toshiba doesn't make identifying what features are being used in each implementation, indeed, I haven't been able to figure just what kind of NAND the iPad 2 is using. So while we know that it is Toshiba NAND and while we suspect that it is 24 nm product, so far we only know for certain that Toshiba is implementing this technology in its embedded SmartNAND products. Reply
  • mcnels1 - Thursday, May 05, 2011 - link

    On what basis is DRAM cheap relative to NAND? Looking at spot prices, the cheapest DRAM is 97 cents per gigabit ($0.97 for DDR3 1Gb 128Mx8), while the cheapest MLC flash is 22 cents per gigabit ($6.93 for MLC Flash 32Gb 4096Mx8). All prices from memoryexchange.com. Even SLC is cheaper than DRAM ($40.78 for SLC Flash 64Gb 8192Mx8 or 64 cents per gigabit). Reply
  • mindless1 - Thursday, May 05, 2011 - link

    It's cheap on the basis of needing less DRAM capacity (512MB for example) to effect a performance increase which is the goal of the larger capacity pseudo-SLC cache in addition to higher reliability.

    Also remember that this pseudo-SLC is actually MLC chips utilizing only half of each block so your price per Gb listed above needs be doubled for a comparison.
    Reply
  • JasonInofuentes - Thursday, May 05, 2011 - link

    Also bear in mind that the DRAM used in these devices isn't the DDR3-2200 helping break PCMark records. This is commoditized high volume, low size RAM designed for these specific applications to be as cheap as possible. Reply
  • MrSpadge - Sunday, November 18, 2012 - link

    That's why he's looking at the ceapest DRAM, not the most expensive.. Reply
  • marc1000 - Thursday, May 05, 2011 - link

    the point is: toshiba already has 18nm in the works. Intel just announced 22nm, but as this news shows, they are NOT "the only ball on the park". Reply
  • sheh - Thursday, May 05, 2011 - link

    CPUs and flash are different things. Reply
  • Iketh - Thursday, May 05, 2011 - link

    IN the park... really, you should never post again Reply
  • jjj - Thursday, May 05, 2011 - link

    do they rotate the space designated as cache? otherwise i imagine the cache would die rather fast.
    also any idea if the size of the "cache"can be dynamically adjusted by the OS?
    Reply
  • JasonInofuentes - Thursday, May 05, 2011 - link

    We asked just these questions when speaking with the reps. To cover the longevity issue, remember that the pseudo-SLC cache really is a lot like SLC, so in addition to its speed its reliability goes up significantly, nothing specific but certainly something approaching an order of magnitude (closer to 30,000 than 3,000 p/e cycles). So the physical blocks that are designated pseudo-SLC remain so unless rewritten by software.

    Further, the best case scenario in terms of reliability is that it is used as a firmware partition in which case it will go through very few cycles over the life of the device. The worst case scenario is that it used as cache and even in that case since it's primary role is as random write cache, assuming a 512MB cache, it would still take an awful lot of random data written (in a typical use scenario) before writing to the entire cache once, let a lone 30,000 times.

    Based on our discussions the size of the cache is determined at the controller level, so while the OS must be aware of this arrangement it is not in control of it. Great questions, keep'em coming. If we don't know we'll ask!
    Reply
  • jjj - Thursday, May 05, 2011 - link

    Thanks for the reply.
    Any chance they are whilling to talk about BiCS and 3D Read/Write?
    Reply
  • FunBunny2 - Thursday, May 05, 2011 - link

    Since the post is about "different kind of NAND", have you gotten any information on what Unity Semiconductor was/is doing? Or any other "better than NAND" replacement? Reply
  • JasonInofuentes - Thursday, May 05, 2011 - link

    @jjj and @FunBunny2, We will get back to you on those questions. Thanks for the replies. Reply
  • sheh - Thursday, May 05, 2011 - link

    "...they expect to see similar endurance as their 24nm products, around 3,000 program/erase cycles. This is owing to ever improving ECC and wear leveling algorithms..."

    Aren't P/E cycles the raw device value, with wear leveling and error correction coming afterwards?
    Reply
  • tygrus - Friday, May 06, 2011 - link

    Are they using the same MLC cells but treating them like SLC in firmware. Write '1' as '11' (actually the default after erase) and '0' as '00'. The reads back the '11' and '10' of MLC cell as a '1' and the '01' and '00' as '0'. It allows the tight tolerances of MLC to be relaxed so the two extremes can still be read even though the signal has moved towards the middle. What would normally fail

    I suppose it's more flexible than adding SLC cells and trying to identify them to the controller or adding SLC chips to the array of channels which might limit bandwidth and cost more.

    Maybe they could put faster/wider SLC (but less blocks) in the controller to use as the write cache to combine writes before erasing a MLC cell.

    They could also slow down the erase (lower voltage but takes longer) to reduce the wear and electron migration/burying so as to increase reliability and the number of erase cycles it can last. If you have enough over-provisioning, garbage collection (cleared blocks ready for use) and trim to allow more free blocks you can mitigate slow erase. Sustained sequential/random write will be a smaller percentage of old peak eg. 20-25% of peak write, 50% of old sustained write.
    Reply
  • RU482 - Tuesday, May 10, 2011 - link

    As NAND die sizes shrink, does temperature have a greater or lesser effect on the life and performance of the circuit?

    To put it another way, would a 19nm NAND be more or less stressed by temperature when compared to a 25nm or 32nm NAND?
    Reply
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  • runeks - Monday, June 13, 2011 - link

    Would be cool to see some benchmarks of this. I suspect it's the iSSD that is used in the Efika MX Smarttop and Smartbook. They have 8GB and 16GB, respectively. But I haven't gotten hold of any benchmarks yet (random read/write). Sandisk website says it's 160 MB/s, 100 MB/s sequential read/write, respectively. Reply

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