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  • Homerr - Wednesday, April 05, 2006 - link

    I keep looking but can't find when AM2 is supposed to be introduced. Can anyone enlighten me? Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    I keep looking but can't find when AM2 is supposed to be introduced. Can anyone enlighten me?

    6/6/06...
    Reply
  • Toadster - Wednesday, April 05, 2006 - link

    The grand opening of Fab 36 was mostly for media attention as the plant would not begin shipping revenue parts until Q1 of 2006. That sometime is today as AMD has just announced that Fab 36 is finally shipping revenue parts.

    Q1 ended last week LOL
    Reply
  • hans007 - Wednesday, April 05, 2006 - link

    i think a lot of it defeinitely is spin doctoring.

    another factor is that the dies are all single core dies which yield higher than dual core ones (since the dual core ones are not seperate like say presler if one of them is bad all of it is bad).

    that said, the way amd make it sound it look slike their capacity will be greatly increased in the future because they can now make smallre chips. which is pretty stupid.

    since even if they go to 65nm by the time 65nm is out everything intel makes will be dual core. so amd will have to sell everything dual core as well. so all the dies will be twice the size making the chips per wafer the same as it is now 90nm @ 300mm.
    Reply
  • MrKaz - Wednesday, April 05, 2006 - link

    That’s a good point.

    But this is only valid if Intel can get bad dual cores into single cores.

    In the case of Presler, Intel for each 2 good chips get 1, so isn’t this the same of getting just one dual?
    Reply
  • coldpower27 - Wednesday, April 05, 2006 - link

    Yileding 2x 81mm2 dies is much easier then yielding AMDs single monolothic Toledo of 199mm2 or Windsor of 220mm2. If there is a defect in the processor core logic the Dual Core is completely useless and has to be thrown out. If it is the cache then they can make a lower cache Dual Core out of it.

    With Cedar Mill/Presler Intel is in a great position to address market needs as that core can be binned in 3 different SKU's.

    Celeron D 35x Cedar Mill 512KB, disable part of the cache.
    Pentium 4 6x1 Cedar Mill.
    Pentium D Presler, 2 fully functioning Cedar Mill cores, from 2 different wafers even.

    Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    Yileding 2x 81mm2 dies is much easier then yielding AMDs single monolothic Toledo of 199mm2 or Windsor of 220mm2

    True...but it really hurts performance.
    Honestly, if it was such an advantageous design financially then why would Intel design Conroe with a shared cache? I don't think the yields are affected as much as the spin doctors at Intel would have you believe...
    Reply
  • coldpower27 - Wednesday, April 05, 2006 - link

    It's not a big deal for Conroe or Allendale, those are 14x mm2 or 11x mm2 in die area, once you get back down to this level on 300mm wafers it's not too too bad.

    The NetBurst design had reached the end of it's life now, since it can't compete on performance effectively, it might as well rake in the advantage of reduced costs, good yeilds and flexibility. Since there isn't a ODMC, there isn't a reason to keep the dies together as NetBurst functions identically if the dies are seperate in Dual Core configuration.

    The Dual Die implementation is an effective one, Intel will be using it for Kentsfield and Clovertown, on the 65nm process. Allowing them to put two Conroes or Woodcrests on a single MCM package. We'll see if it affects performance on Core Architecture negatively to the degree that it will uncompetitive. There is more then one way to extract performance.






    Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    It's not a big deal for Conroe or Allendale, those are 14x mm2 or 11x mm2 in die area, once you get back down to this level on 300mm wafers it's not too too bad

    So you're saying that once AMD gets to 65nm they will have better percentage yields because it will be a smaller die?
    quote:

    Since there isn't a ODMC, there isn't a reason to keep the dies together as NetBurst functions identically if the dies are seperate in Dual Core configuration

    Can't say I agree here...
    The only advantage to "joining" the dice (either through DCMA or shared cache) is cache coherency and avoiding the FSB.
    quote:

    We'll see if it affects performance on Core Architecture negatively to the degree that it will uncompetitive. There is more then one way to extract performance

    Since Kentsfield will be for the desktop and Quad Core Opterons will be Socket F only, the one to watch will be Cloverton. Frankly it won't be the MCM as much as the lack of a P2P platform that will make Cloverton as ineffective as Paxville is...that said, if you look at the difference in core scaling on AMD vs Intel in the single to dual core market (or in this case DCMA vs MCM), you'll see exactly what I'm talking about.
    Reply
  • coldpower27 - Thursday, April 06, 2006 - link

    quote:

    Since Kentsfield will be for the desktop and Quad Core Opterons will be Socket F only, the one to watch will be Cloverton. Frankly it won't be the MCM as much as the lack of a P2P platform that will make Cloverton as ineffective as Paxville is...that said, if you look at the difference in core scaling on AMD vs Intel in the single to dual core market (or in this case DCMA vs MCM), you'll see exactly what I'm talking about.


    Like I said I am gonna wait and see on Clovertown, it might be an issue, though again it might not. Funny you choose the worst NetBurst Dual Core as your example..., I am just gonna wait till I see the results in the server market. Paxville has access to a much older platform however, so I don't really take results to be of much use.

    quote:

    So you're saying that once AMD gets to 65nm they will have better percentage yields because it will be a smaller die?


    No I don't think so, when AMD gets to 65nm, they won't beat Intel in the die size department, an optical shrink of Windsor to 65nm Brisbane, would be from 220mm2 to 132mm2. It would also depend if it's a straight shrink or if AMD adds more features and what not to their cores. I expect their yeilds to drop some from a mature 90nm SOI process, but total yield should be somewhat better.

    I guess I should be more clear, the die sizes for Conroe/Allendale are fine as they are for Intel on a 65nm process that has been in production for at least 2Q.

    quote:

    TextCan't say I agree here...
    The only advantage to "joining" the dice (either through DCMA or shared cache) is cache coherency and avoiding the FSB.

    How do you disagree again, as NetBurst doesn't have shared cache, not at the consumer level at least, so they communicate through the FSB anyway. Since the NetBurst design communicates through the FSB, the DUal Die implementation is fine...
    Reply
  • Viditor - Thursday, April 06, 2006 - link

    quote:

    Funny you choose the worst NetBurst Dual Core as your example

    Because it's their only dual core x86 server chip...so it's pretty much the only example possible.
    quote:

    Paxville has access to a much older platform however, so I don't really take results to be of much use

    You can extrapolate results by comparing Paxville to Nocona (since it's just a Nocona MCM...)
    quote:

    when AMD gets to 65nm, they won't beat Intel in the die size department, an optical shrink of Windsor to 65nm Brisbane, would be from 220mm2 to 132mm2. It would also depend if it's a straight shrink or if AMD adds more features and what not to their cores


    I'm confused here. I'm sure you're not saying that as both are at 65nm, Conroe will be smaller than Brisbane...that would be silly as it has double the cache. Also, if you look at current die pictures of AM2, you'll notice that the same amount of cache is significantly smaller on Rev F than it was on Rev E (i.e. AMD has drastically improved their cache density).
    IIRC, this began with you repeating some of the Intel marketing stuff about MCMs being a much more economical way to produce chips, but the fact that Conroe wasn't using it was irrelevant (i.e. it wouldn't reduce their yields) because they are smaller...

    As to AMD's yields, they have stated many times over the last 3 months that 65nm will START at the same yields that current 90nm chips enjoy (mature yields). They have even shown how this is possible with APM and given an example with their 90nm process which was close to mature yields at it's launch.
    quote:

    How do you disagree again, as NetBurst doesn't have shared cache, not at the consumer level at least, so they communicate through the FSB anyway. Since the NetBurst design communicates through the FSB, the DUal Die implementation is fine...

    I disagreed with your comment about the ODMC making a difference. I don't believe there is anything inherent in the NetBurst uA that precludes it from being a true dual core (either with a shared cache or DCA)...except of course that Intel didn't plan for it. Therefore (as you say), for NetBurst chips, MCMs were the only possible way to go. IMHO, the "yield advantage" is just Intel's way of "making lemonade"...
    I still see no reason why NGMA cores will fare any better with MCM than their NetBurst brethren did.

    This brings up a last point...will AMD go MCM as well? Most of us are assuming that they will continue with DCA for their cores, but all of the Hammers have been DC designs since the very beginning. I have no idea as to whether or not the AMD Quad Cores are true quads or MCMs. If anybody knows for a fact one way or another, please post!
    Reply
  • coldpower27 - Thursday, April 06, 2006 - link

    I am not gonna have to take extrapolations using NetBurst architecture as a template as pretty much useless. The FSB bandwidth avaialble to Core Architecture will be significantly enhanced in comparison to what Paxville or Nocona has access to.

    The NetBurst Architecture is too bandwidth dependent to serve as a good indicator of how Core Architecture will react.

    I am saying Intel will have an advantage with Allendale vs Brisbane 2 processors with equal amount of total LV2 cache. Not in relation to Conroe. With Conroe it is unknown as it would be a fairly mature product by that timeframe, so it's hard to compare yield between AMD and Intel.

    The definition of mature yields has been vague to me at best, perhaps it means that entering into the 65nm process they will have equal to greater output then can be had on the mature 90nm process going out... Not an issue really for desktops till H1 2007 however. Indications look like AMD will try to concentrate on the server and mobile segements with their 65nm production.

    "True Dual Core" your actually spouting that AMD propaganda??? Dual Core says there only has to be 2 cores, their isn't anything in the definition that limits it to a monolitic die vs MCM module. Presler is no less "true" then Toledo, maybe you should stick to the monolithic vs MCM argument instead of using vague terminology as "true".
    It's common knowledge that a smaller die is easier to yield then a larger one on a given process, it simply a matter of more surface area for a defect to occur. Your opinion of the making lemonade part is jsut that your opinion which I don't agree with, NetBurst Dual Core designs wasn't amazing as it wasn't design to be a Dual Core that is true from what Intel has spoken on the subject, but the solution cranked out was an acceptable one for something that had no intention of moving to Dual Core.

    There isn't a point in making a monolithic design for NetBurst now as Intel is moving to a more integrated design like AMD did, where the two cores work more closely like in Conroe with Shared LV2. Why spend resources to improve the old NetBurst Architecture, when you have sometihng much better in the works.

    Well a surprise for you is that Tulsa the Xeon MP core will based based on Netburst MicroArchitecture and will have access to 16MB of Shared LV3 cache.

    Can AMD go MCM at all? I mean with how closely their cores are working together with their ODMC shared between the two cores.

    It won't matter in the end though, we'll get monolithic quad core designs out of Intel on the 45nm node when it's more economical to do so and hence having the ability for each core to work more closely with the other 3. The 65nm versions are just first interations to wet the peoples appetite for better quad cores as we go down the road.

    I am not saying a MCM design is great for performance either, but it's important to see how adversely Core Architecture will be affected, since even going through a FSB that is 1.33GHZ is alot better then the 800MHZ FSB that Paxville's platform was stuck with. I am all for a monolithic die package Quad Core when economically feasable, but a MCM design in the meantime is an adequate solution to introduce Quad Core.





    Reply
  • Viditor - Thursday, April 06, 2006 - link

    quote:

    I am not gonna have to take extrapolations using NetBurst architecture as a template as pretty much useless

    Not for determining the penalty that MCM incurs it isn't...though it would be for determining the exact performance of Kentsfield (we haven't actually benched them yet).
    quote:

    The FSB bandwidth avaialble to Core Architecture will be significantly enhanced in comparison to what Paxville or Nocona has access to

    It's true that Intel will be increassing the FSB from 800MHz to 1333MHz (an increase of 40%), but for quad core you will also be increasing the number of cores by 100%...
    quote:

    Dual Core says there only has to be 2 cores

    Sorry, but where does it "say" that? Both "Dual" and "Twin" mean 2...however Dual implies identical and connected while twin implies not connected but identical. Doesn't it make more sense and seem clearer to call an MCM a "twin" core for clarification?
    quote:

    the solution cranked out was an acceptable one for something that had no intention of moving to Dual Core

    We shall have to agree to disagree then...IMHO, the twin core solution did allow Intel to save a bit of face, but as their sales and reviews of twin core CPUs was so dismal, I would hardly call it acceptable.
    quote:

    Can AMD go MCM at all? I mean with how closely their cores are working together with their ODMC shared between the two cores

    That's assuming a single ODMC...just as Intel is going to a 2 FSB model, AMD could use a dual ODMC model on quad core. Then, all they would need is a cHT link between the cores (just as like it is between cores on current Opteron MP chips). This would solve a problem and create one.
    1. Latency for cache coherency would increase, but only slightly
    2. memory bandwidth would double per CPU
    A main advantage over Intel though is that it would be a cHT link rather than arbitration through the FSB...just hypothesizing here.
    Reply
  • MrKaz - Wednesday, April 05, 2006 - link

    Yes but i still tell you the same:

    For each 1000 processor cores build intel sells 500 processors... half of production, is also a huge hit. I'm not saying AMD implementation is better...

    Celeron is only 256kb cache not 512kb.
    Reply
  • coldpower27 - Wednesday, April 05, 2006 - link

    I was talking the Cedar mill revision, that will be released soon, right now they are still based on Prescott so 256KB yes, the Cedar Mill version will be 512kb.

    Intel sells 500 Dual Cores, or it could be 250 Dual Cores and 500 Single Cores, it depends on market needs.
    Reply
  • her34 - Wednesday, April 05, 2006 - link

    what's intel's total production capacity? Reply
  • logeater - Tuesday, April 04, 2006 - link

    Poor AMD. All this spin doctoring has left them to dizzy to actually know what they are doing. The AM2 will struggle to get anywhere near Conroe if you are smart enough read between the lines.

    Time to take out my stocks in AMD and pump them into Intel me thinks. ;)

    Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    Time to take out my stocks in AMD and pump them into Intel me thinks

    Cool...that'll be me on the other end of that transaction! :)
    Reply
  • MrKaz - Wednesday, April 05, 2006 - link

    Well Intel in the last 3 years has been lagging behind Intel. What’s the problem if Intel leaves AMD behind during some months or a year or two?

    That doesn’t mean Intel is superior. Right now still seems inferior to me...
    Reply
  • MrKaz - Wednesday, April 05, 2006 - link

    Well Intel in the last 3 years has been lagging behind AMD. Reply
  • Calin - Wednesday, April 05, 2006 - link

    Yes, AMD's stock might go down some - and Intel's stock might go up. By the improvements they have now for the AM2 socket and DDR2, I think AMD won't stomp all over Intel this time - and might even be at a performance disadvantage. Even if Intel gets to equal performance with AMD, it will be a hit against AMD (but maybe not so much for Intel).
    So, it might be good to sell AMD stocks and wait for a better time - some time before AMD transition to 65nm. Buying Intel... I wouldn't
    Reply
  • Griswold - Wednesday, April 05, 2006 - link

    I would be worried (if I had any AMD stocks) if Intel actually had something on the server front to compete. It doesnt matter what woodcrest looks like in 6-9 months, customers in the corporate server world arent early adopters. They will stick to Opterons and netburst Xeons for at least a year. This is where AMD sees their biggest profit gain in the next few years - and rightfully so.

    And while I cant stand the Inquirer, if its true that the K8L core for the Opteron sports twice the FPU units, woodcrest might indeed have more than just one problem to be competitive in quite a few server business segments.

    With that said, if Opteron sales keep growing, AMDs shares wont likely go down. They might not keep going up as they did over the last years, even if AMD has no good answer to conroe anytime soon. But thats just the desktop market, which has taken the backseat on their priority list some time ago, in favor of server and mobile segments.
    Reply
  • Calin - Thursday, April 06, 2006 - link

    Yes, I guess a big part of AMD production capacity could be absorbed into the server/workstation market, where prices are the greatest (and profits too). I don't know the ratio between workstation/server market and desktop market, but especially considering the decrease in desktop market (in favor of laptop), AMD really can leave the desktop market undefended.
    They will have a hard time competing in the low power laptop market - even if in the high performance laptop market they are doing fine.
    Reply
  • phaxmohdem - Tuesday, April 04, 2006 - link

    Or you could dump it into GM. I hear they're doing well ;) Reply
  • DSaum - Tuesday, April 04, 2006 - link

    Since your so called conroe review where you showed your Intel bias, why do you expect AMD to tell you anything substantive about their plans or processes?
    Reply
  • coldpower27 - Tuesday, April 04, 2006 - link

    Just because they showed AMD in a really unfaouvrable doesn't mean their Intel biased. It means AMD has to get it's ass up and actually try to compete for a change. Not just sit their charging tons of money for their Dual Cores. Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    Not just sit their charging tons of money for their Dual Cores

    Huh? Their Dual cores are cheap! If you compare price/performance to Intel, they are only a fraction of the cost...
    Just because AMD doesn't make super-low-end Dual Cores is no reason to call the ones they make expensive...
    While this may change (or not) at a future date, it certainly is the case now.
    Reply
  • Questar - Thursday, April 06, 2006 - link

    No, they are not cheap.

    PD 805 is $110 - retail with HSF.

    What's AMD got that cheap? A Sempron?
    Reply
  • Viditor - Thursday, April 06, 2006 - link

    quote:

    What's AMD got that cheap? A Sempron?

    Yes, exactly...a Sempron that most assuredly outperforms the 805. Of course that wouldn't be the case for the few who overclock, but they are a miniscule portion of the market.
    Dual core doesn't always mean faster...
    Reply
  • Questar - Friday, April 07, 2006 - link

    Yeah, a Sempron can out perform a dual core P4.

    Dude, statements like that just destroy your credibility.
    You should give it a rest.
    Reply
  • Viditor - Friday, April 07, 2006 - link

    quote:

    Yeah, a Sempron can out perform a dual core P4

    Of course it can...don't you read reviews?
    If you read http://www.xbitlabs.com/articles/cpu/display/sempr...">this X-Bit review (granted there aren't a lot of reviews on Sempron), you'll see it runs neck and neck (and in many cases better) with the A64 3000+ which Anand directly compared to the 805 http://www.anandtech.com/cpuchipsets/showdoc.aspx?...">here.
    As Anand said in his conclusion:
    "Gamers looking for a temporary upgrade should honestly look to the Athlon 64 3000+ instead, as very few games have boarded the dual train as of now"..."if you are a multitasker or run multithreaded applications, and you want a great low cost solution, then the Pentium D 805 makes a wonderful stepping stone to a future AM2 or Conroe platform. If you're a gamer that doesn't care about multitasking while gaming, the Athlon 64 3000+ is still a strong value"

    In addition, if you look at the power usage page of Anand's review, you'll note that the 805 requires a power plant of it's own...:) (j/k)
    Reply
  • blackbrrd - Tuesday, April 04, 2006 - link

    Bullshit ;)

    Anandtech was one of the first review sites to match the Opteron up vs the Xeon, which showed Opteron spanking Xeons. Haven't seen anything like those reviews from any other sites.
    Reply
  • hans007 - Tuesday, April 04, 2006 - link

    they have used a lot of vague terminology.

    i.e. our wafer yields at 300mm are equal to 200mm.

    that means, what?

    that they get the same number of cpus out of 300mm and 200mm. or the percenteage of the wafer yield?

    they also have no 65nm demos at all even though they claim to be sampling the cpus. and they claim 40% better transistor performance, but that probably just means it say uses up less power not switching faster.

    so it all depends on just the exact details of what that all means.

    Reply
  • AnnonymousCoward - Saturday, April 08, 2006 - link

    "Yield" refers to the percentage of good die.

    40% better transistor performance isn't merely talking about power. Performance means performance. It's also not saying the CPU is going to be 40% faster. There's propagation delays involved with transistor circuits, and some low level figure will be sped up by 40% (I don't know if it's rise/fall times, propagation delay, switching frequency, etc).
    Reply
  • Calin - Wednesday, April 05, 2006 - link

    As a 300mm wafer has more than twice the size of a 200mm wafer, they should produce twice as much processors from a 300mm wafer. Maybe more, as less space is lost on the sides.

    Anyway, why they don't make the wafers square? that would decrease the area lost on sides
    Reply
  • stephenbrooks - Thursday, April 06, 2006 - link

    quote:

    Anyway, why they don't make the wafers square? that would decrease the area lost on sides
    I think they should make the chips round.
    Reply
  • Zoomer - Sunday, April 09, 2006 - link

    That will be even worse, unless 1 chip == 1 wafer. And that's insane. Reply
  • eetnoyer - Wednesday, April 05, 2006 - link

    I guess you don't know how wafers are made. The silicon is originally made sort of like homemade rock candy (Put a string tied to a pencil into a jar of hot, sugar-saturated water) and thus comes out in a columnar shape (I know, very rough analogy). After that, the wafers are made by taking slices off of the column. I suppose they could square the columns before slicing, but then there would be alot of waste, the cost of which would still be passed onto the chip maker. Much more efficient to just get that extra production out of the circular wafer.....it doesn't really cost any extra. Reply
  • Calin - Thursday, April 06, 2006 - link

    No, I didn't knew. Thanks for the explanation.
    I remember I heard about diamond "wafers" that were made by growing a rectangular substrate - and once it was thick enough, they would cut it in several smaller slices. The result would be a "brick". I somehow assumed silicon would be the same
    Reply
  • menting - Tuesday, April 04, 2006 - link

    exactly what I was thinking.
    also, that's comparing the 300mm and 200mm wafers at 90nm process only, which isn't too much of a feat to accomplish.
    when the 300mm goes to 65nm process, the yield (% die/waf) will definitely go down some, how much we probably will never know. it could go down enough that a 300mm wafer will initially produce only about the same or a little more number of dies per wafer than the 200mm at 90nm does.

    Basically this announcement regarding yields isn't saying much except for the expected.
    Reply
  • coldpower27 - Tuesday, April 04, 2006 - link

    Which isn't surprising exact yield information is cirtical information to Intel and AMD. Hence they are careful to be very vague on the issue. Reply
  • rqle - Tuesday, April 04, 2006 - link

    any update to the The AM2 Story blog. would like to know where the performance level of am2 chipset w/ ddr2, hope for major in improvement over what you said in that blog. Reply
  • mesyn191 - Wednesday, April 05, 2006 - link

    He stated pretty clearly they're getting a approx. 5% performance increase at the same clock bd AM2 A64's, and that there may be other improvements as well. Reply
  • defter - Wednesday, April 05, 2006 - link

    quote:

    He stated pretty clearly they're getting a approx. 5% performance increase at the same clock


    He stated clearly that performance increase is 5% or LOWER using DDR2-800. This would indicate about 2-3% performance increase on average using DDR2-800 and 0-1% increase using DDR2-667.
    Reply
  • Ecmaster76 - Tuesday, April 04, 2006 - link

    "The parts that it is shipping are 90nm Athlon 64 and Sempron CPUs, so Opterons and Athlon 64 X2s will still come out of Fab 30 next door."

    Read: FAB 30 is handling the expensive/complex bins; FAB 36 is doing the cheap n easy parts while yields are being improved.

    "AMD cites customer demand as the reason that Athlon 64 and Sempron are first out of the new fab, which honestly makes sense; there's always need for more capacity at the lower end."

    Read:All the chips they can make are being sold as Opterons 'cause thats where the margins are. As a result the demand for cheap chips is being ignored. Therefore, more capacity == $$$$ (bank baby!)

    (long live 939!)
    Reply
  • Calin - Wednesday, April 05, 2006 - link

    AMD sells what market needs. Their purpose is to sell all the processors they can produce at the highest price they can. If they increase price, the market will buy less, and if that leaves them with warehouse surplus they are losing.
    They might "force" on the market the perception that the Opteron 939 chips are better than the Athlons64, as selling them is better overall (more $$$ for AMD)
    Reply
  • fikimiki - Tuesday, April 04, 2006 - link

    Because FAB30 is ramping 30,000 wspm and FAB36 is ramping up to 17,000wspm by the end of 2006. FAB36 wafers are LARGER (300mm) and Chatered Corp. will be doing 5000 wspm for AMD - this means ~2x more CPUs by the end of 2006.

    40% better transistor performance at 65nm means 3,8-4GHz CPU. How about that? :)
    Reply
  • coldpower27 - Tuesday, April 04, 2006 - link

    The only true part here is that AMD's Fab 30 is having 30K WSPM on 200mm Wafers.

    AMDs Fab 36 is going to ramp up to 20K WSPM by 2008 on 300mm Wafers. That part is true. No idea where you pulled 17k WSPM by end of 2006 from.

    40% Better transistor performance doesn't equal a 40% increase in clock frequency, that is flat out absurd.
    Reply
  • Viditor - Wednesday, April 05, 2006 - link

    1. Chartered is at 2000wspm on 300mm and 50%+ yields on AMD processors by July.
    http://www.fabtech.org/index.php?option=content&am...">Fabtech article Since that is 300mm, it is equivalent to 4000wspm on 200mm. Chartered is expected to be at 18,000wspm by years end.
    http://techreport.com/onearticle.x/9688">Techreport
    2. Fab 30 is at 30,000wspm on 200mm and yields in the 60-80% range (rumour and based on statements in conference calls).
    3. Fab 36 is estimated to be at 26,000wspm by years end on 300mm (which is = 52,000wspm on 200mm). Even if they hit only HALF that number, that's still more than double last year's production for AMD by this year's end...
    Reply
  • Questar - Wednesday, April 05, 2006 - link

    Dude, you said three posts up that there aren't any estimates for production at fab 36, and here you said there are.

    Make up your mind.
    Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    Dude, you said three posts up that there aren't any estimates for production at fab 36, and here you said there are

    No, I said AMD hadn't released any estimates...this article was not from AMD.
    Reply
  • fikimiki - Wednesday, April 05, 2006 - link

    Hector Ruiz said:http://www.fabtech.org/index.php?option=content&am...">Here:

    "Our latest projections average out certain factors, but we feel it is not unreasonable for Fab 36 to have 26,000wspm by the end of 2006. Then depending on a host of factors, fab capacity would be reached sometime in the 1H07."

    And because of 65nm transitions they have to lower a production output to ~17wspm. Fab36 was not designed to have smaller production output than FAB30 - for sure...

    Reply
  • coldpower27 - Wednesday, April 05, 2006 - link

    26K WSPM by end of 2006? When AMD is claiming 20K WSPM by 2008, don't you find that somewhat odd? Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    26K WSPM by end of 2006? When AMD is claiming 20K WSPM by 2008, don't you find that somewhat odd?


    That would be the old numbers...AMD has increased the efficiency of their Fabs. For example, Fab30 was originally to max out at 20k wspm and now does 30k. AFAIK, AMD has not released current capacity estimates for Fab 36.
    Reply
  • Questar - Wednesday, April 05, 2006 - link

    "To ameliorate some of the financial risks, AMD will not completely build out the facility just yet. As it stands now, AMD can start production on 13,000 silicon wafers a month. Enough empty space, however, exists to crank that up to 20,000 wafer starts a month. Getting to the 100 million mark will involve populating the current empty space in the 13,400-square-meter plant with equipment."

    http://news.com.com/With+new+factory%2C+AMD+ups+an...">http://news.com.com/With+new+factory%2C.../2100-10...
    Reply
  • Viditor - Wednesday, April 05, 2006 - link

    It doesn't really matter, but the article is from the Grand Opening in October.
    The key point here is the number 15,000wspm. That represents (on 300mm) a doubling of capacity. By this years end, between Fab 36 and Chartered we will most likely see a tripling of capacity.
    Reply
  • coldpower27 - Wednesday, April 05, 2006 - link

    Well since this article was released later, I am going to go with what is here as more accurate, I don't see any reason to beleive the Fabtech document versus what is written here. Reply
  • defter - Wednesday, April 05, 2006 - link

    quote:

    Hector Ruiz said:Here


    No he didn't. That article contains guesses and estimates of fabtech.org and according to their page, that article is already quite old. For example they are talking about ramp starting in Q1 although shipments only began in Q2.
    Reply
  • Viditor - Wednesday, April 05, 2006 - link

    quote:

    they are talking about ramp starting in Q1 although shipments only began in Q2

    Actually, the ramp began at the end of Q4 05...it takes about 3 months for shipping product after a ramp begins.
    Reply
  • mesyn191 - Wednesday, April 05, 2006 - link

    Yea, I'd be suprised if we saw more than a 20% clockspeed improvement over .90 chips assumig the .65 chip is just a die shrink with no clocspeed optimizations made of course. Reply
  • coldpower27 - Wednesday, April 05, 2006 - link

    Yeah considering AMD has gotten only 15% so far from 90nm DSL SOI, considering they make 3.00GHZ of ocurse. Reply
  • BaronMatrix - Tuesday, April 04, 2006 - link

    Intel showed NO INCREASE WHEN GOING TO DDR2, so how is AMD slacking if they DON'T get 10-20% increase? Reply
  • defter - Wednesday, April 05, 2006 - link

    Because Intel's chips were FSB limited and couldn't take advantage of full bandwidth that DDR2 offered. AMD's chip can utilize full bandwidth because of integrated memory controller. Reply
  • creathir - Tuesday, April 04, 2006 - link

    Horray! He lives! At least AM2 is finally starting to look more like a "next gen" platform than it has in the past.
    - Creathir
    Reply
  • ncage - Tuesday, April 04, 2006 - link

    Isn't ibm helping them out some in this department? Reply
  • bob661 - Tuesday, April 04, 2006 - link

    Good to see them working on 45nm. Hopefully, the next transition will be closer together with Intel. Competition is good. Reply
  • Furen - Tuesday, April 04, 2006 - link

    The problem is that the actual transition to a new manufacturing process requires a pretty hefty investment. I'm sure AMD has been able to go 65nm for a while now, it just cant afford to do so. Reply
  • mesyn191 - Wednesday, April 05, 2006 - link

    No, they've been waiting on tools from other manufacturers + validating thier VHDL libraries. In fact that is why FAB36 is starting out with .90 production instead of .65, AMD wants to get some revenue from it ASAP and since thier .65 stuff is still on order they have to work with what they've got instead. Reply

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