quote:I keep looking but can't find when AM2 is supposed to be introduced. Can anyone enlighten me?
quote:Yileding 2x 81mm2 dies is much easier then yielding AMDs single monolothic Toledo of 199mm2 or Windsor of 220mm2
quote:It's not a big deal for Conroe or Allendale, those are 14x mm2 or 11x mm2 in die area, once you get back down to this level on 300mm wafers it's not too too bad
quote:Since there isn't a ODMC, there isn't a reason to keep the dies together as NetBurst functions identically if the dies are seperate in Dual Core configuration
quote:We'll see if it affects performance on Core Architecture negatively to the degree that it will uncompetitive. There is more then one way to extract performance
quote:Since Kentsfield will be for the desktop and Quad Core Opterons will be Socket F only, the one to watch will be Cloverton. Frankly it won't be the MCM as much as the lack of a P2P platform that will make Cloverton as ineffective as Paxville is...that said, if you look at the difference in core scaling on AMD vs Intel in the single to dual core market (or in this case DCMA vs MCM), you'll see exactly what I'm talking about.
quote:So you're saying that once AMD gets to 65nm they will have better percentage yields because it will be a smaller die?
quote:TextCan't say I agree here...
The only advantage to "joining" the dice (either through DCMA or shared cache) is cache coherency and avoiding the FSB.
quote:Funny you choose the worst NetBurst Dual Core as your example
quote:Paxville has access to a much older platform however, so I don't really take results to be of much use
quote:when AMD gets to 65nm, they won't beat Intel in the die size department, an optical shrink of Windsor to 65nm Brisbane, would be from 220mm2 to 132mm2. It would also depend if it's a straight shrink or if AMD adds more features and what not to their cores
quote:How do you disagree again, as NetBurst doesn't have shared cache, not at the consumer level at least, so they communicate through the FSB anyway. Since the NetBurst design communicates through the FSB, the DUal Die implementation is fine...
quote:I am not gonna have to take extrapolations using NetBurst architecture as a template as pretty much useless
quote:The FSB bandwidth avaialble to Core Architecture will be significantly enhanced in comparison to what Paxville or Nocona has access to
quote:Dual Core says there only has to be 2 cores
quote:the solution cranked out was an acceptable one for something that had no intention of moving to Dual Core
quote:Can AMD go MCM at all? I mean with how closely their cores are working together with their ODMC shared between the two cores
quote:Time to take out my stocks in AMD and pump them into Intel me thinks
quote:Not just sit their charging tons of money for their Dual Cores
quote:What's AMD got that cheap? A Sempron?
quote:Yeah, a Sempron can out perform a dual core P4
quote:Anyway, why they don't make the wafers square? that would decrease the area lost on sides
quote:He stated pretty clearly they're getting a approx. 5% performance increase at the same clock
quote:Dude, you said three posts up that there aren't any estimates for production at fab 36, and here you said there are
quote:26K WSPM by end of 2006? When AMD is claiming 20K WSPM by 2008, don't you find that somewhat odd?
quote:Hector Ruiz said:Here
quote:they are talking about ramp starting in Q1 although shipments only began in Q2