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  • ceefka - Sunday, April 03, 2005 - link

    I assume this wafer and die stacking will also be used for increasing the GB's per RAM-stick. What else when 64-bit OSs and apps have become the standard? Is there any word from memory manufacturers on that? Reply
  • Athlex - Saturday, April 02, 2005 - link

    AMD seems to be missing the point of pitting Turion against Centrino. Intel's Centrino package requires a P-M, Intel chipset, and Intel wireless. Since most people don't know the diff between P-M and Centrino it's a brilliant way for Intel to move more silicon.

    Also confusing why AMD is using the same packaging for Turion CPUs as they do for normal A64 CPUs. The lowest-power XP-Ms use the smaller socket 563 (Sharp and Averatec systems for example). AMD already has a spec for a smaller 'socket 638' A64, seems like that should be the thin and light version.. C'mon AMD, let's see a real thin and light K8 notebook!
    Reply
  • suryad - Friday, April 01, 2005 - link

    I agree...I cant wait for a dual core FX proc with each core clocked @ 3 GHz...think what a monster system that would be...yikes!! Reply
  • ceefka - Friday, April 01, 2005 - link

    #23 What exactly is ILP/TLP ?

    ILP Instruction Level Parallism
    TLP Thread Level Parallism

    It is explained in one of the CPU articles here on AT.

    Happy surfing.
    Reply
  • BlvdKing - Friday, April 01, 2005 - link

    #26 - I would be torn between an IBM notebook and Turion too. IBM notebooks are amazing - full of features and so durable. Reply
  • cryptonomicon - Thursday, March 31, 2005 - link

    incredibly interesting article by anand.

    it seems like this is the kind of stuff you can only find at anantech.. the info is so in depth right from the source.
    Reply
  • Regs - Thursday, March 31, 2005 - link

    Thank's Anand. With all this Intel news running about, it's good to see AMD isn't just planning to be a bench warmer. Reply
  • Xunilla - Thursday, March 31, 2005 - link

    #25 -- I agree, that is making a generalization that doesn't necessarily apply across the board. Reply
  • Xunilla - Thursday, March 31, 2005 - link

    Reply
  • phaxmohdem - Thursday, March 31, 2005 - link

    I really want to see what kind of Turion notebooks spring forth. It will take a lot though to change my decision on the IBM T42 as my next notebook though. Reply
  • stephenbrooks - Thursday, March 31, 2005 - link

    I'm a bit confused by the terminology in places. Doesn't ILP mean "Instruction-Level Parallelism", i.e. that applies to distributing instructions between different execution units, and perhaps other tricks like out-of-order execution, branch prediction etc. But it certainly does NOT include "frequency", as seems to be implied by the first page! Unless it means that the longer pipeline will be interpreted as more parallelism (which is true). But that's not the only way to increase clock speed... a lot comes from the process technology itself. Reply
  • MrEMan - Thursday, March 31, 2005 - link

    I just realized that the link to "IDF Spring 2005 - Predicting Future CPU Architecture Trends" requires that you go to the next page, and not the one the link points to, and it is there where ILP/TLP is explained. Reply
  • MrEMan - Thursday, March 31, 2005 - link

    What exactly is ILP/TLP ? Reply
  • sphinx - Thursday, March 31, 2005 - link

    #12 PeteRoy

    I would have to agree with you.
    Reply
  • Son of a N00b - Thursday, March 31, 2005 - link

    Great article Anand! I feel better informed and this was something that filled up my little spot of curiosity I had saved for the future of processors.


    It seems as if AMD will continue to keep up the great work. I will be a customer for a long time.
    Reply
  • hectorsm - Thursday, March 31, 2005 - link

    blckgrffn I did not see your post until now. Your explanation seem to make a lot of sense. I guess is now a matter of opinion to how much is "30%" worth in terms of heat and transistor.

    thanks.
    Reply
  • hectorsm - Thursday, March 31, 2005 - link

    Thanks Filibuster. The article confirms the up to 30% gain in processing power under certain multithreaded scenarios. But I am still confused to why this is a waste of resources specially when HT was design for multiple thread use.

    Reply
  • blckgrffn - Thursday, March 31, 2005 - link

    The point of hyperthreading being a waste of resources is that it costs A LOT to put features like that into hardware, and the die space and tranistors used to do HT could probably have been used in better way to create a more consistent performance gain, or could have been left out all together, reducing the complexity, size, power use/heat output of the processor and putting a little bit more profit per chip sold at the same price into Intels pocket. That is why it is a misuse of resources.

    Nat
    Reply
  • BLHealthy4life - Thursday, March 31, 2005 - link

    Just release the FX57 already... Reply
  • hectorsm - Thursday, March 31, 2005 - link

    "not sure what you mean by "processing efficiency". all HT does is virtually separate the processor into two threads. maybe I'm missing something, but I can't figure out why everyone associates HT with performance gain. "

    There are supposedly fewer misprediction in the pipeline since there are two threads sharing the same pipes. Even when the total processing power is cut in halth, the sum of the two appears to be greater with HT. It has been reported up to 30% increase in total output when running two intances of folding@home and HT.

    So I am still wondering why Fred is calling it a "misuse of resources". Maybe he knows something we don't. It would be interesting to know more about this. Maybe someone at AnandTech get get a clarification from Fred?
    Reply
  • Filibuster - Thursday, March 31, 2005 - link

    ...but...its HYPER!

    #11 it can also decrease performance by 10-50% depending on the application. Clearly it matters what you're doing with your PC.

    http://www.digit-life.com/articles/pentium4xeonhyp...

    I think Fred is talking about the inconsistant gains/losses. Its not the best way to spend transistors.
    Reply
  • fitten - Thursday, March 31, 2005 - link

    #13, HT is kind of like hardware allowing context switching at instruction speed levels. Tyipcally, a thread that stalls on IO (like a hard drive) or something gets swapped out and another thread runs until the IO request completes. However, if a thread just can't use a cache well (streaming data, for example) all of those stalls due to memory loads just cause the CPU to sit and wait. These stalls are on the order of 10s of clock cycles. Other IO is on the order of 1000s of clock cycles (or more). A context switch is on the order of 100s of clock cycles. Obviously, you don't want to swap threads just because of a L2 cache miss. However, HT allows two thread contexts to be loaded so that when one thread stalls on a L2 cache miss, for example, the other thread can execute instructions with no delay. It's like shuffling cards. Basically, it allows the CPU to execute two contexts on the granularity of a clock cycle or two rather than on 100s of clock cycles.

    So, as an example, the worst case for a thread is that every piece of data it wants will generate an L2 cache miss. On a non-HT processor, this means that this thread will not be swapped out until its scheduling quantum is met. But, during that time, the CPU will in effect be idle for probably 90% of the time due to all the cache misses. Since the thread won't be swapped out, your CPU will effectively be used for only 10% of the time during that quantum, then the next thread is allowed to run. With HT, both threads are loaded and those 90% of the cycles that the "bad" thread would waste can actually be used by the other thread.
    Reply
  • xtknight - Thursday, March 31, 2005 - link

    #11-not sure what you mean by "processing efficiency". all HT does is virtually separate the processor into two threads. maybe I'm missing something, but I can't figure out why everyone associates HT with performance gain. Reply
  • PeteRoy - Thursday, March 31, 2005 - link

    The future of processors is Software that make use of them. Reply
  • hectorsm - Thursday, March 31, 2005 - link

    Does anyone know why Fred thinks that HT is a misuse of resources?

    Doesn't HT increase processing efficiency by 10-30%?

    Sounds to me like he got it backward.
    Reply
  • xsilver - Thursday, March 31, 2005 - link

    Could it be that possibly the reason for the slowdown in clock increases is not due to AMD/Intel R&D but rather software companies that are not keeping up.... As far back as I can remember many programs were able to utilize the new speed increases effectivly whereas now, a budget "3000" cpu is already kinda overkill for many office apps....
    gaming is the only arena where the software is pushing the hardware (maybe video editing too but that market is much smaller?)

    there needs to be more innovation on the software front to utilize the added hardware benefits... is a positive reinforncement routine....
    If there was that push, I have no doubt that the speed increases would happen at a much better rate
    Reply
  • Calin - Thursday, March 31, 2005 - link

    An architecture with several cores, with one more powerful than the others, requests the programmer to tell to each thread what kind of performance it needs. While this could be accepted by console developers (that work very close to the hardware layers), you can say bye bye to easy porting to that platform.
    while the performance increase can be substantial, the trade off is very specific code even at the highest level
    Reply
  • Jeff7181 - Thursday, March 31, 2005 - link

    Comment WAS mad on HT...

    "Fred’s response to this question was thankfully straight forward; he isn’t a fan of Intel’s Hyper Threading in the sense that the entire pipeline is shared between multiple threads, in Fred’s words 'it’s a misuse of resources.'"
    Reply
  • Zebo - Thursday, March 31, 2005 - link

    Wish some comment was made on HT, intel only real saving grace for last couple years. Guess with DC it becomes a non-issue though at that point.


    Hehe nice to see CPU world going full circle... AMD copied Intel like nobodies biz now it's the other way around. Props to AMD for innovating dispite thier punny size.. they definity should be rewarded by sales. I know I made the right choice with A64, the latency he mentions you can feel all the time, hard to "benchmark" it other than system just feels snappy compared to any other CPU I've used to including a P4C oC'ed to 3.4, A-XP OCed to 2.7, and IBM chips from apple at 2.5.
    Reply
  • bupkus - Thursday, March 31, 2005 - link

    Reduced processor complexity is a step neither manufacturer is willing to take.
    OR
    Neither manufacturer appears willing to reduce processor complexity.
    Reply
  • bersl2 - Thursday, March 31, 2005 - link

    #1: Thank you for the paralepsis. Reply
  • Googer - Thursday, March 31, 2005 - link

    I have set up the OFFICIAL SOVIET RUSSIA thread in the forums section, so we can keep this garbage out of the news section.

    Let the bad humor fly here:

    http://forums.anandtech.com/messageview.aspx?catid...
    Reply
  • oupei - Thursday, March 31, 2005 - link

    should be:

    "it's clear that sacrificing hardware complexity isn't a sacrifice that EITHER amd OR intel are (IS?) willing make"

    or

    "it's clear that sacrificing hardware complexity IS a sacrifice that neither amd nor intel are (IS?) willing make"

    or how about just writing a sentence that is easier to understand...
    Reply
  • ksherman - Thursday, March 31, 2005 - link

    "It’s clear that sacrificing hardware complexity isn’t a sacrifice that neither AMD nor Intel are willing to make..."

    Or not so clear... what exactly does this mean?
    Reply
  • Bonesdad - Thursday, March 31, 2005 - link

    I was going to say "first post" but i won't Reply

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