POST A COMMENT

28 Comments

Back to Article

  • IntelUser2000 - Tuesday, September 14, 2004 - link

    Ah crap. Posted empty message.

    Anyways, in response to:
    "That's what I like about the Athlon 64, no stupid large caches necessary"

    One major thing that people get wrong is that "Imagine Athlon64 or Opteron with 24MB cache". The thing is, AthlonXP and Opteron/Athlon64 didn't get much benefit from cache anyway as Pentium 4 did. We didn't see significant improvements going to Barton with 512KB L2 cache compared to P4, which had much larger performance improvements(Barton Link: http://www.anandtech.com/cpuchipsets/showdoc.aspx?... Pentium 4 Northwood Link: http://www.anandtech.com/cpuchipsets/showdoc.aspx?...

    Comment from Barton review at last page:"It is very interesting to note the relatively small performance improvement that resulted from the additional L2 cache, at least when you compare the impact of Barton to the impact Northwood had on the Pentium 4."

    If you look at the reviews, there are times where Barton is basically equal to the Thoroughbred B core, even considering that Thoroughbred B has 3.8% higher clock than Barton, doubling of L2 cache from 256KB to 512KB didn't do much as 512KB cache did on P4.

    So if AMD puts the current Itanium's 6MB L3, not only there won't be a significant performance increase, the performance scaling would rapidly decrease. That's the reason why S754 Sempron isn't much worse than full-blown Athlon64 with double L2 cache. So even if AMD has the resources or the will to put 6MB L2, it won't benefit Opteron/A64 much.

    Look at this link: http://www.anandtech.com/cpuchipsets/showdoc.aspx?...

    I mean, how can two processors that are targeted at such different markets, Sempron for value and A64 for mainstream, and cache size, have such little difference in performance? Why get A64 2800+ Newcastle when Sempron does same with 1/2 the price? So I say AMD will be lucky to get 10-15% performance increase by going to 24MB cache at this scaling.

    It's not the ability of AMD to put 24MB L2 or L3 cache that's the problem, its the performance that's squeezed out of that.

    Itaniums however(especially with Montecito), love bandwidth like Pentium 4's and Xeons and since Montecito is Dual-core, 2 thread per core(it's called Switch on Event Multithreading, which is different from Simultaneous Multithreading which Intel calls Hyperthreading), double the L2 cache of Madison9M's cache and some will be VERY useful.

    By the way, Montecito performance figures are 1.5x-2.0x PER core, with same 400MHz bus speed as Madison said here, and is rumored to have a version that's available with 18GB/sec FSB and memory bandwidth, from the current 6.4GB/sec: http://www.realworldtech.com/forums/index.cfm?acti...

    Thanks for reading(if you did anyway).
    Reply
  • IntelUser2000 - Tuesday, September 14, 2004 - link

    Reply
  • JarredWalton - Friday, September 10, 2004 - link

    #25 - I think I saw something from AMD that suggested that software should be licensed per socket in the future. Obviously, MS will do what they feel is in their best interest, but license fees per socket would be nice.

    #23 - There *are* drawbacks to having an integrated memory controller, and Hypertransport probably doesn't boost speed in single processor installations much at all. Anyway, Intel certainly has had some difficulties of late witht their CPU design. What I'm saying, though, is that their manufacturing facilities are probably the best around, with IBM coming in second.
    Reply
  • plk21 - Thursday, September 09, 2004 - link

    So, how will this affect Microsoft's Per Processor licensing on SQL Server? Will I have to buy 2 licenses per processor? Now I'm running it on Hypertrhreaded chips, only with 1 license per physical chip...
    Reply
  • PsharkJF - Thursday, September 09, 2004 - link

    #21
    I wasn't saying that Intel's helping them, I'm saying that Intel is being AMD's guinea pig :P
    #22
    ------
    One fine day Intel might come back with a vengeance and show us someting that beats the crap out of AMD64
    ------
    Dual pentium M with onboard memory controller *drool*
    Reply
  • ceefka - Thursday, September 09, 2004 - link

    What puzzles me is, when they are so "ahead of the game", why didn't they too come up with the idea of an onboard mem-controller and something like Hypertransport or Hypertransport itself? If you see what it does for AMD64's and Opterons, imagine what it could do for a Prescott or Xeon. No Sir, they just slap on extra cache, pump the FSB some more and leave the darn thing screaming for bandwith. In my view they are also a little complacent.

    One fine day Intel might come back with a vengeance and show us someting that beats the crap out of AMD64 or Opteron. That's what I've been thinking for almost 6 months now... If only AMD would sit still for a minute ;-)
    Reply
  • JarredWalton - Thursday, September 09, 2004 - link

    #21 - Actually, that's not at all correct, unless you think that Intel is sending over their people to help AMD out with getting their 90 nm up and running? IBM might do that, but not Intel. :p AMD is also still using 200 mm wafers, which is seriously behind the state of the art. Basically, AMD started investing in their 90 nm plant 2+ years ago, so they weren't waiting for Intel to have problems and work them out. They're starting construction of a 65 nm plant as well, which will finally get them 300 mm wafers. AMD still makes a great chip, but honestly Intel is ahead on several key areas of manufacturing technology. Reply
  • PsharkJF - Thursday, September 09, 2004 - link

    #13
    ------
    You can make a case for some issues with their designs of late, but as far as technology? We've seen 90 nm parts from Intel for almost a year now (more if you count early samples), while AMD is only just starting to ship them.
    ------
    In other words, AMD is playing it smart and letting Intel work out the kinks in the technology for them before they spend any money doing things that may not work well.
    Also consider that Intel needs smaller dies due to higher clockspeed requirements.
    Reply
  • 8NP4iN - Wednesday, September 08, 2004 - link


    the message is clear

    intel has failed
    Reply
  • PrinceGaz - Wednesday, September 08, 2004 - link

    I dread to guess at just how expensive those Montecito's with 1.7 billion transistors would cost. Probably quite a bit more than the $400 or so I'm looking to spend on my next CPU, I reckon :) Reply
  • Lonyo - Wednesday, September 08, 2004 - link

    We knew that they woul dhave 24MB of cache a while ago.
    There was a post on the Anandtech forums asking why you would need such a large amount of cache.
    Reply
  • kherman - Wednesday, September 08, 2004 - link

    So, am I the only one that noticed that EACH PROCESOR HAS 24 MEG OF CACHE ON IT!

    First image on page 3:
    http://www.anandtech.com/tradeshows/showdoc.aspx?i...
    Reply
  • ysrgrathe - Wednesday, September 08, 2004 - link

    iCube is supposed to be presenting their NMP-5000A network media player at the IDF. They won an award last year for their NMP-4000 model, which has also received a lot of positive reviews. I'm interested to know more; iCube has nothing on their site other than a press release about the IDF presentation an a picture showing dual antennas.

    From last year's timeline I would expect the product to launch around Christmas; would be nice to have some info before then. Anyone at the convention hear anything?
    Reply
  • JarredWalton - Wednesday, September 08, 2004 - link

    ^^^ This is why you shouldn't do drugs, kids. Reply
  • AMDjihad - Wednesday, September 08, 2004 - link

    AHAHAH> INtel loses like a faceusut. AHAHA. Whorlovas. Intel loses. I agrre witgb alkb of you. Intel sucks. HAHAHA> OPertin ins bwext at everythoing. Hah wether simulation.s I can do that. HAhahha. Reply
  • TrogdorJW - Wednesday, September 08, 2004 - link

    #12 - Itanium 2 can issue up to 8 instructions per clock, but stalls on one set of instructions can still occur. If you have hyper-threading, you have more potential to fill all of the available issue slots. That's why the POWER5 chip from IBM also has a version of hyperthreading, although I believe IBM calls it "symmetric multi-threading" (SMT). Oh, and Itanium also has more FP/SSE execution units than the P4/Xeon, which is why it has such "kick booty FP".

    #8 - That really didn't make much sense, partly due to the incorrect use of the Enter key. But let's address this: "Intel has not had a demonstrable lead in design or manufacturing in several years. They have only been maintaining parity with the competition. They intially argued against the need for .13 micron and smaller die shrink, they followed the lead of IBM and AMD. And followed again when copper replaced aluminum in the CPU." Ugh, where to begin...

    Okay, let's make this clear. Intel has never argued against .13 micron or any other process shrinks. They have said at times that it was not necessary *YET*, and that they would pursue it in the future. This happened with copper interconnects (AMD used them in .18 micron while Intel waited until late in their .13 micron use), and it happened with x86-64. Don't confuse "we aren't doing that yet" with "we aren't pursuing that *ever*".

    You can make a case for some issues with their designs of late, but as far as technology? We've seen 90 nm parts from Intel for almost a year now (more if you count early samples), while AMD is only just starting to ship them. IBM went with SOI first and Intel went with strained silicon. They're both pushing the process technology in different ways. To say Intel hasn't been perfect is absolutely valid, but to say they're failing completely (which seems to be the gist of your post) is taking it way too far.

    Just my opinion here, of course.
    Reply
  • mkruer - Tuesday, September 07, 2004 - link

    The only advantade that the Itanic has in computer operations is that is has a kick booty FP operation. problem is that most progrmas use limited floating point. on top of that I would not be to supprised to see the FP core migrating into the Xeon, or what ever intel is going to call their next gen chip Reply
  • sprockkets - Tuesday, September 07, 2004 - link

    Big deal, 1.7 billion transistors, probably 95% of that is just cache memory.

    Again, why would Itaniums need Hyperthreading? If your EPIC code alreay is made to process so many instructions at once in parallel, then how is hypthreading going to make any difference?
    Reply
  • ksherman - Tuesday, September 07, 2004 - link

    sorry, my post was intended for #8 not #9 Reply
  • ksherman - Tuesday, September 07, 2004 - link

    ^ half that didnt make sense...
    and I am sure that 4 dual core opterons could probably do real time weather simulations too, its not an Intel exclusive capability...
    Reply
  • idgaf13 - Tuesday, September 07, 2004 - link

    Can we just be try to be objective when analyzying the data ?
    I expect "more" from the Intels and IBMs
    in the industry.
    The volume and prowess of their engineering departments should be an awesome force to reckon with.
    Intel has not had a demonstrable lead in design or manufacturing in several years.
    They have only been maintaining parity with the competition.
    They intially argued against the need for 13 micron and smaller die shrink ,they followed the lead of IBM and AMD. And followed again when copper replaced aluminum in the CPU.
    RDRAM and Itanium 2 good ideas ?
    I have seen no benefit as a result of them.
    The die shrink and change of substrate have definitely benefited the user.
    Intels marketing sounds more and more like a
    MS marketing campaign and less like a demonstration of engineering prowess.
    I certainly hope the balance of the IDF will yield some demonstrations of engineering prowess that Intel has.
    To think that they are intimidated to the point of not releasing info is amazing to me.
    Reply
  • Questar - Tuesday, September 07, 2004 - link

    #5,

    Look at the slides, they say dual core desktop in 2005.

    Why demo a sual core p4, they just showed a chip 1.7 billion transistors. There's no point in showing a p4 when you have the big gun on stage.

    Get back to me when you're doing real time weather simulation on an AMD chip, okay?
    Reply
  • Night201 - Tuesday, September 07, 2004 - link

    I have that National Geographic issue shown on Page 3. That's so cool! It's a great article if anyone can read it. Maybe I'll scan it one day. Reply
  • Falloutboy - Tuesday, September 07, 2004 - link

    as I figured no dual core p4 or P-M demonstration. I think 2005 is going to be a long shot for them if they don't even have anything to show now. Only reason I can think other than they really are BSing how far they are on a desktop dual core chip is that its not what we all expect and they don't want to give AMD the heads up too early Reply
  • DerekWilson - Tuesday, September 07, 2004 - link

    Sorry bout that. the network went down right before I could hit post on the third page. but the net finally came back up and now all is well. Reply
  • Saist - Tuesday, September 07, 2004 - link

    ah, there's page 3.

    For a while I was wondering if Anandtech was acting out a scene from SpaceBalls.
    Reply
  • sprockkets - Tuesday, September 07, 2004 - link

    I guess the article is still in progress.

    That's what I like about the Athlon 64, no stupid large caches necessary.
    Reply
  • mcveigh - Tuesday, September 07, 2004 - link

    wheres page 3? Reply

Log in

Don't have an account? Sign up now