The most challenging part of last year's iPhone 5s review was piecing together details about Apple's A7 without any internal Apple assistance. I had less than a week to turn the review around and limited access to tools (much less time to develop them on my own) to figure out what Apple had done to double CPU performance without scaling frequency. The end result was an (incorrect) assumption that Apple had simply evolved its first ARMv7 architecture (codename: Swift). Based on the limited information I had at the time I assumed Apple simply addressed some low hanging fruit (e.g. memory access latency) in building Cyclone, its first 64-bit ARMv8 core. By the time the iPad Air review rolled around, I had more knowledge of what was underneath the hood:

As far as I can tell, peak issue width of Cyclone is 6 instructions. That’s at least 2x the width of Swift and Krait, and at best more than 3x the width depending on instruction mix. Limitations on co-issuing FP and integer math have also been lifted as you can run up to four integer adds and two FP adds in parallel. You can also perform up to two loads or stores per clock.

With Swift, I had the luxury of Apple committing LLVM changes that not only gave me the code name but also confirmed the size of the machine (3-wide OoO core, 2 ALUs, 1 load/store unit). With Cyclone however, Apple  held off on any public commits. Figuring out the codename and its architecture required a lot of digging.

Last week, the same reader who pointed me at the Swift details let me know that Apple revealed Cyclone microarchitectural details in LLVM commits made a few days ago (thanks again R!). Although I empirically verified many of Cyclone's features in advance of the iPad Air review last year, today we have some more concrete information on what Apple's first 64-bit ARMv8 architecture looks like.

Note that everything below is based on Apple's LLVM commits (and confirmed by my own testing where possible).

Apple Custom CPU Core Comparison
  Apple A6 Apple A7
CPU Codename Swift Cyclone
ARM ISA ARMv7-A (32-bit) ARMv8-A (32/64-bit)
Issue Width 3 micro-ops 6 micro-ops
Reorder Buffer Size 45 micro-ops 192 micro-ops
Branch Mispredict Penalty 14 cycles 16 cycles (14 - 19)
Integer ALUs 2 4
Load/Store Units 1 2
Load Latency 3 cycles 4 cycles
Branch Units 1 2
Indirect Branch Units 0 1
FP/NEON ALUs ? 3
L1 Cache 32KB I$ + 32KB D$ 64KB I$ + 64KB D$
L2 Cache 1MB 1MB
L3 Cache - 4MB

As I mentioned in the iPad Air review, Cyclone is a wide machine. It can decode, issue, execute and retire up to 6 instructions/micro-ops per clock. I verified this during my iPad Air review by executing four integer adds and two FP adds in parallel. The same test on Swift actually yields fewer than 3 concurrent operations, likely because of an inability to issue to all integer and FP pipes in parallel. Similar limits exist with Krait.

I also noted an increase in overall machine size in my initial tinkering with Cyclone. Apple's LLVM commits indicate a massive 192 entry reorder buffer (coincidentally the same size as Haswell's ROB). Mispredict penalty goes up slightly compared to Swift, but Apple does present a range of values (14 - 19 cycles). This also happens to be the same range as Sandy Bridge and later Intel Core architectures (including Haswell). Given how much larger Cyclone is, a doubling of L1 cache sizes makes a lot of sense. 

On the execution side Cyclone doubles the number of integer ALUs, load/store units and branch units. Cyclone also adds a unit for indirect branches and at least one more FP pipe. Cyclone can sustain three FP operations in parallel (including 3 FP/NEON adds). The third FP/NEON pipe is used for div and sqrt operations, the machine can only execute two FP/NEON muls in parallel.

I also found references to buffer sizes for each unit, which I'm assuming are the number of micro-ops that feed each unit. I don't believe Cyclone has a unified scheduler ahead of all of its execution units and instead has statically partitioned buffers in front of each port. I've put all of this information into the crude diagram below:

Unfortunately I don't have enough data on Swift to really produce a decent comparison image. With six decoders and nine ports to execution units, Cyclone is big. As I mentioned before, it's bigger than anything else that goes in a phone. Apple didn't build a Krait/Silvermont competitor, it built something much closer to Intel's big cores. At the launch of the iPhone 5s, Apple referred to the A7 as being "desktop class" - it turns out that wasn't an exaggeration.

Cyclone is a bold move by Apple, but not one that is without its challenges. I still find that there are almost no applications on iOS that really take advantage of the CPU power underneath the hood. More than anything Apple needs first party software that really demonstrates what's possible. The challenge is that at full tilt a pair of Cyclone cores can consume quite a bit of power. So for now, Cyclone's performance is really used to exploit race to sleep and get the device into a low power state as quickly as possible. The other problem I see is that although Cyclone is incredibly forward looking, it launched in devices with only 1GB of RAM. It's very likely that you'll run into memory limits before you hit CPU performance limits if you plan on keeping your device for a long time.

It wasn't until I wrote this piece that Apple's codenames started to make sense. Swift was quick, but Cyclone really does stir everything up. The earlier than expected introduction of a consumer 64-bit ARMv8 SoC caught pretty much everyone off guard (e.g. Qualcomm's shift to vanilla ARM cores for more of its product stack).

The real question is where does Apple go from here? By now we know to expect an "A8" branded Apple SoC in the iPhone 6 and iPad Air successors later this year. There's little benefit in going substantially wider than Cyclone, but there's still a ton of room to improve performance. One obvious example would be through frequency scaling. Cyclone is clocked very conservatively (1.3GHz in the 5s/iPad mini with Retina Display and 1.4GHz in the iPad Air), assuming Apple moves to a 20nm process later this year it should be possible to get some performance by increasing clock speed scaling without a power penalty. I suspect Apple has more tricks up its sleeve than that however. Swift and Cyclone were two tocks in a row by Intel's definition, a third in 3 years would be unusual but not impossible (Intel sort of committed to doing the same with Saltwell/Silvermont/Airmont in 2012 - 2014).

Looking at Cyclone makes one thing very clear: the rest of the players in the ultra mobile CPU space didn't aim high enough. I wonder what happens next round.

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  • trifster - Monday, March 31, 2014 - link

    Makes that PA Semi buy look darn smart now doesn't it. Reply
  • quadrivial - Tuesday, April 01, 2014 - link

    This chip seems to share quite a bit in common with P.A. Semi’s POWER-based PA6T-1682M from a few years ago. The question that nobody seems to ask is how Apple beat ARM to the punch by almost 18 months in the high-performance arena. Nobody's that much better than ARM at ARM designs.

    Two answers come to mind. The first is that Apple made the ARM64 spec and told ARM to use it otherwise Apple switches to MIPS or POWER. The second is that Apple has an existing design that can be repurposed. It so happens that this is also somewhat true (in the PA6T-1682M designed in '05). Perhaps both of these are true.
    Reply
  • llukspur - Monday, March 31, 2014 - link

    I love when things start to come together:
    What was Bob Mansfield doing in semi conductors' "ambitious plans for the future"?
    Why is the A7 intensely overpowered for a phone?
    Why did Apple make even its pro machine the size of a table-top jug?
    What reason will Intel exist in teh consumer space in 5 years?
    Reply
  • toyotabedzrock - Tuesday, April 01, 2014 - link

    It would have been nice if you could have put up a diagram for ARM'S vanilla 64bit core the a57 Reply
  • FunBunny2 - Tuesday, April 01, 2014 - link

    exactly. Reply
  • Anders CT - Tuesday, April 01, 2014 - link

    " Looking at Cyclone makes one thing very clear: the rest of the players in the ultra mobile CPU space didn't aim high enough. "

    Really? There is certainly a place for large, wide, out-of-order architectures, but ultra mobile does not seem the most natural fit. I mean, there is a reason that Intel cannot compete with Mediatek in mobile, and it is not because of lack of performance, or lack of 64-bit adressing.

    If it was really true that the A7 was a desktop-class chip, it would be pretty ridiculous to put it inside of a smartphone.
    Reply
  • OreoCookie - Tuesday, April 01, 2014 - link

    I find arguments akin to »this is too powerful for a phone« a bit misguided: if programmers have that much horse power at their disposal, they'll use it. And if it is only used to reduce input lag, it's a win for the user. Reply
  • Anders CT - Tuesday, April 01, 2014 - link

    Sure, performance is always useful. But wide, out-of-order CPU's comes with a large cost in sillicon and powerconsumption.

    What I am saying is that if the Apple A7 had been a 3-wide 32-bit design, it would have ha
    Reply
  • Anders CT - Tuesday, April 01, 2014 - link

    ...had very good performance with smaller die area and power-consumption. Reply
  • OreoCookie - Tuesday, April 01, 2014 - link

    According to battery life tests here at Anandtech and elsewhere, the A7 did not fare worse than the A6, so I don't see an argument for worse battery life. Sure, if you run the A7 at full kilter, perhaps it will shorten the battery life, but such a workload isn't what you'd usually find on a smartphone or a tablet. Your argument regarding die area doesn't make sense to me, the A7 is smaller than the A6X by about 20 % and only about 6 % larger than the A6. Yes, the A7 is manufactured as a smaller process node, but in terms of area, it's comparable or smaller. Moreover, Apple doesn't need to make a profit on its SoC. Also, die area has nothing to do with the 64 bit-ness of the CPU (the Cortex A53 is a comparatively small ARMv8 CPU core).

    I don't see any indication that Apple has had to pay a penalty for making the A7 the way it is. I have the impression you're trying hard to make the argument that the A7 is not a good design (»large cost increase«, »increased power consumption«) and argue that it is not »desktop class«.

    I'm glad Apple has stirred up the competition, I'm curious to see how the Denver-based Tegra K1 performs compared to the A7 and A8.
    Reply

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