Cortex A15: GPU Power Consumption - 3D Gaming Workload

ARM's Mali-T604 GPU is pretty quick, but similar to ARM's Cortex A15s it can definitely use a considerable amount of power to deliver that performance. Peak GPU power consumption tops out at just under 4W compared to ~1W for Qualcomm's Adreno 225. Even the Cortex A15s pull a decent amount of power in this test compared to the alternatives. It seems like that 4W max we keep seeing is likely the typical TDP for the Exynos 5250, anywhere from 1x - 4x what we get with Atom Z2760 and APQ8060A.

Task Energy - 3D Game 1 - Total Platform

Task Energy - 3D Game 1 - CPU Only

Task Energy - 3D Game 1 - GPU Only

The Mali-T604's performance advantage here comes at a price: total energy consumed is far higher than any of the competing solutions.

GPU Power Consumption - Max, Avg, Min Power

Max Power Draw - 3D Game 1 - Total Platform

Max Power Draw - 3D Game 1 - GPU Only

Max Power Draw - 3D Game 1 - CPU Only

Average Power Draw

Average Power Draw - 3D Game 1 - Total Platform

Average Power Draw - 3D Game 1 - GPU Only

Average Power Draw - 3D Game 1 - CPU Only

Minimum Power Draw

Min Power Draw - 3D Game 1 - Total Platform

Min Power Draw - 3D Game 1 - GPU Only

Min Power Draw - 3D Game 1 - CPU Only

Cortex A15: WebXPRT 2013 - Community Preview 1 Determining the TDP of Exynos 5 Dual
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  • A5 - Friday, January 4, 2013 - link

    Even if you just look at the Sunspider (which draws nothing on the screen) power draw, it's pretty clear that the A15 draws more power. There have been a ton of OEMs complaining about A15's power draw, too.
  • madmilk - Friday, January 4, 2013 - link

    Since when did screen resolution matter for CPU power consumption on CPU benchmarks? Platform power might change, yes, but this doesn't invalidate many facts like Cortex-A15 using twice as much power on average compared to Krait, Atom or Cortex-A9.
  • Wolfpup - Friday, January 4, 2013 - link

    Good lord. Do you have some evidence for any of this? If neither Windows nor Android is the "right platform" for ARM, then...are you waiting for Blackberry benchmarks? That's a whole lot of spin you're doing, presumably to fit the data to your preconceived "ARM IS BETTER!" faith.
  • Veteranv2 - Friday, January 4, 2013 - link

    Hahaha, the Nexus 10 has almost 4 times the pixels of the Atom.
    And the conclusion is it draws more power in benchmarks? Of course, those pixels aren't going to fill itself. Way to make conclusion.

    How big was that Intel PR cheque?
  • iwod - Saturday, January 5, 2013 - link

    While i wouldn't say it was a Intel PR, I think they should definitely have left the system level power usage out of the questions. There is no point telling me that a 100" Screen with ARM is using X amount of power compared to 1" Screen with Haswell.

    It is confusing.

    But they did include CPU and GPU benchmarks. So saying it is Intel PR is just trolling.
  • AlB80 - Friday, January 4, 2013 - link

    Architectures with variable length of instruction are doomed. Actually there is only one remains. x86.
    Intel made the step into a happy past when CISC has an advantage over RISC, when superscalarity was just a theory.
    Cortex A57 is coming. ARM cores will easily outperform Atom by effective instruction rate with minimum overhead.
  • Wolfpup - Friday, January 4, 2013 - link

    How is x86 doomed when it has an absolute stranglehold on real PCs, and is now competitive on ultramobile platforms?

    The only disadvantage it holds is the need for a larger decoder on the front end, which has been proportionally shrinking since 1995.
  • djgandy - Friday, January 4, 2013 - link

    plus effing one!

    I think some people heard their uni lecturers say something once in 1999 and just keep repeating it as if it is still true!
  • AlB80 - Friday, January 4, 2013 - link

    Shrinking decoder... nice myth. Of course complicated scheduler and ALU dozen impact on performance, but do not forget how decoded instruction queues are filled. Decoder is only one real difference.
    1. There is fundamental limits how many variable instructions can be decoded per clock. CISC has an instruction cross-interference at the decoder stage. One logical block should determine a total length of decoded instructions.
    2. There is a trick when CISC decoder is disintegrated into 2-3 parts with dedicated inputs, so its looks like a few independent decoders, but each part can not decode any instruction.

    Now compare it with RISC.
    And as I said, what happens when Cortex can decode 4,5,6,7,8 instructions?
  • Kogies - Friday, January 4, 2013 - link

    Don't be so quick to prophesy the death of a' that. What happens when a Cortex decodes 8 instructions... I don't know, it uses 8W?

    Also, didn't Apple choose CISC (Intel) chips over RISC (PowerPC)? Interestingly, I believe Apple made the switch to Intel because the PowerPC chips had too high a power premium for mobile computers.

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