CPU Architecture Improvements: Background

Despite all of this platform discussion, we must not forget that Haswell is the fourth tock since Intel instituted its tick-tock cadence. If you're not familiar with the terminology by now a tock is a "new" microprocessor architecture on an existing manufacturing process. In this case we're talking about Intel's 22nm 3D transistors, that first debuted with Ivy Bridge. Although Haswell is clearly SoC focused, the designs we're talking about today all use Intel's 22nm CPU process - not the 22nm SoC process that has yet to debut for Atom. It's important to not give Intel too much credit on the manufacturing front. While it has a full node advantage over the competition in the PC space, it's currently only shipping a 32nm low power SoC process. Intel may still have a more power efficient process at 32nm than its other competitors in the SoC space, but the full node advantage simply doesn't exist there yet.

Although Haswell is labeled as a new micro-architecture, it borrows heavily from those that came before it. Without going into the full details on how CPUs work I feel like we need a bit of a recap to really appreciate the changes Intel made to Haswell.

At a high level the goal of a CPU is to grab instructions from memory and execute those instructions. All of the tricks and improvements we see from one generation to the next just help to accomplish that goal faster.

The assembly line analogy for a pipelined microprocessor is over used but that's because it is quite accurate. Rather than seeing one instruction worked on at a time, modern processors feature an assembly line of steps that breaks up the grab/execute process to allow for higher throughput.

The basic pipeline is as follows: fetch, decode, execute, commit to memory. You first fetch the next instruction from memory (there's a counter and pointer that tells the CPU where to find the next instruction). You then decode that instruction into an internally understood format (this is key to enabling backwards compatibility). Next you execute the instruction (this stage, like most here, is split up into fetching data needed by the instruction among other things). Finally you commit the results of that instruction to memory and start the process over again.

Modern CPU pipelines feature many more stages than what I've outlined here. Conroe featured a 14 stage integer pipeline, Nehalem increased that to 16 stages, while Sandy Bridge saw a shift to a 14 - 19 stage pipeline (depending on hit/miss in the decoded uop cache).

The front end is responsible for fetching and decoding instructions, while the back end deals with executing them. The division between the two halves of the CPU pipeline also separates the part of the pipeline that must execute in order from the part that can execute out of order. Instructions have to be fetched and completed in program order (can't click Print until you click File first), but they can be executed in any order possible so long as the result is correct.

Why would you want to execute instructions out of order? It turns out that many instructions are either dependent on one another (e.g. C=A+B followed by E=C+D) or they need data that's not immediately available and has to be fetched from main memory (a process that can take hundreds of cycles, or an eternity in the eyes of the processor). Being able to reorder instructions before they're executed allows the processor to keep doing work rather than just sitting around waiting.

Sidebar on Performance Modeling

Microprocessor design is one giant balancing act. You model application performance and build the best architecture you can in a given die area for those applications. Tradeoffs are inevitably made as designers are bound by power, area and schedule constraints. You do the best you can this generation and try to get the low hanging fruit next time.

Performance modeling includes current applications of value, future algorithms that you expect to matter when the chip ships as well as insight from key software developers (if Apple and Microsoft tell you that they'll be doing a lot of realistic fur rendering in 4 years, you better make sure your chip is good at what they plan on doing). Obviously you can't predict everything that will happen, so you continue to model and test as new applications and workloads emerge. You feed that data back into the design loop and it continues to influence architectures down the road.

During all of this modeling, even once a design is done, you begin to notice bottlenecks in your design in various workloads. Perhaps you notice that your L1 cache is too small for some newer workloads, or that for a bunch of popular games you're seeing a memory access pattern that your prefetchers don't do a good job of predicting. More fundamentally, maybe you notice that you're decode bound more often than you'd like - or alternatively that you need more integer ALUs or FP hardware. You take this data and feed it back to the team(s) working on future architectures.

The folks working on future architectures then prioritize the wish list and work on including what they can.

Other Power Savings & The Fourth Haswell The Haswell Front End
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  • kylewat - Tuesday, February 12, 2013 - link

    Why is Appl the largest market cap company in the world? Reply
  • Spunjji - Thursday, October 18, 2012 - link

    Fuckwit. Reply
  • nirmalv - Sunday, October 07, 2012 - link

    Anandtech being a hardware site,its more inclined to keenly flow hardware devices with new architecture and innovations. iphone brings in
    1, A new A7 chip design and a novel 3 core graphics core
    2, A new 3 microphone parabolic sound receiving design(which likely will become the new standard)
    3, A new sim tray design(which will also likely become the new standard)
    4, New sony BSI stacked sensor (the 13 mpx version will likely be the rage next year).
    5, The first time that we have a 32 nm LTE chip which will give all day usage.
    6, New thinner screen with incorporated touch panel and 100 % RGB

    I am not sure about samsung but can anyone enlighten me about S3's technical achievements?
    Reply
  • nirmalv - Sunday, October 07, 2012 - link

    Sorry make that a 28 nm LTE baseband Reply
  • centhar - Sunday, October 07, 2012 - link

    99.998% of iPhone users just don't care about that. Really they don't.

    Geeks like me who do, are too damn smart to sell our souls to the such a god damned, locked down and closed system to even bother to care.
    Reply
  • Magik_Breezy - Sunday, October 14, 2012 - link

    2nd that Reply
  • Spunjji - Thursday, October 18, 2012 - link

    3rd Reply
  • CaptainDoug - Tuesday, October 23, 2012 - link

    4th, Reply
  • solipsism - Tuesday, October 09, 2012 - link

    Of course a company that releases one device per product category per year as well as one with the greatest mindshare is going to have more articles.

    But what happens when you add up all Samsung phones against all Apple phones in a given year?

    What happens when you don't count the small blogs that only detail a small aspect of a secretive product but count the total words to get a better feel for the effort spent per company's market segment?

    I bet you'll find that AT spends a lot more time covering Samsung's phones than Apple's.
    Reply
  • Spunjji - Thursday, October 18, 2012 - link

    This. I generally trust their editorial, but the focus on Apple prevails. One just has to read accordingly. Reply

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