Decoupled L3 Cache

With Nehalem Intel introduced an on-die L3 cache behind a smaller, low latency private L2 cache. At the time, Intel maintained two separate clock domains for the CPU (core + uncore) and a third for what was, at the time, an off-die integrated graphics core. The core clock referred to the CPU cores, while the uncore clock controlled the speed of the L3 cache. Intel believed that its L3 cache wasn't incredibly latency sensitive and could run at a lower frequency and burn less power. Core CPU performance typically mattered more to most workloads than L3 cache performance, so Intel was ok with the tradeoff.

In Sandy Bridge, Intel revised its beliefs and moved to a single clock domain for the core and uncore, while keeping a separate clock for the now on-die processor graphics core. Intel now felt that race to sleep was a better philosophy for dealing with the L3 cache and it would rather keep things simple by running everything at the same frequency. Obviously there are performance benefits, but there was one major downside: with the CPU cores and L3 cache running in lockstep, there was concern over what would happen if the GPU ever needed to access the L3 cache while the CPU (and thus L3 cache) was in a low frequency state. The options were either to force the CPU and L3 cache into a higher frequency state together, or to keep the L3 cache at a low frequency even when it was in demand to prevent waking up the CPU cores. Ivy Bridge saw the addition of a small graphics L3 cache to mitigate this situation, but ultimately giving the on-die GPU independent access to the big, primary L3 cache without worrying about power concerns was a big issue for the design team.

When it came time to define Haswell, the engineers once again went to Nehalem's three clock domains. Ronak (Nehalem & Haswell architect, insanely smart guy) tells me that the switching between designs is simply a product of the team learning more about the architecture and understanding the best balance. I think it tells me that these guys are still human and don't always have the right answer for the long term without some trial and error.

The three clock domains in Haswell are roughly the same as what they were in Nehalem, they just all happen to be on the same die. The CPU cores all run at the same frequency, the on-die GPU runs at a separate frequency and now the L3 + ring bus are in their own independent frequency domain.

Now that CPU requests to L3 cache have to cross a frequency boundary there will be a latency impact to L3 cache accesses. Sandy Bridge had an amazingly fast L3 cache, Haswell's L3 accesses will be slower.

The benefit is obviously power. If the GPU needs to fire up the ring bus to give/get data, it no longer has to drive up the CPU core frequency as well. Furthermore, Haswell's power control unit can dynamically allocate budget between all areas of the chip when power limited.

Although L3 latency is up in Haswell, there's more access bandwidth offered to each slice of the L3 cache. There are now dedicated pipes for data and non-data accesses to the last level cache.

Haswell's memory controller is also improved, with better write throughput to DRAM. Intel has been quietly telling the memory makers to push for even higher DDR3 frequencies in anticipation of Haswell.

Feeding the Beast: 2x Cache Bandwidth in Haswell TSX
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  • kylewat - Tuesday, February 12, 2013 - link

    Why is Appl the largest market cap company in the world? Reply
  • Spunjji - Thursday, October 18, 2012 - link

    Fuckwit. Reply
  • nirmalv - Sunday, October 07, 2012 - link

    Anandtech being a hardware site,its more inclined to keenly flow hardware devices with new architecture and innovations. iphone brings in
    1, A new A7 chip design and a novel 3 core graphics core
    2, A new 3 microphone parabolic sound receiving design(which likely will become the new standard)
    3, A new sim tray design(which will also likely become the new standard)
    4, New sony BSI stacked sensor (the 13 mpx version will likely be the rage next year).
    5, The first time that we have a 32 nm LTE chip which will give all day usage.
    6, New thinner screen with incorporated touch panel and 100 % RGB

    I am not sure about samsung but can anyone enlighten me about S3's technical achievements?
    Reply
  • nirmalv - Sunday, October 07, 2012 - link

    Sorry make that a 28 nm LTE baseband Reply
  • centhar - Sunday, October 07, 2012 - link

    99.998% of iPhone users just don't care about that. Really they don't.

    Geeks like me who do, are too damn smart to sell our souls to the such a god damned, locked down and closed system to even bother to care.
    Reply
  • Magik_Breezy - Sunday, October 14, 2012 - link

    2nd that Reply
  • Spunjji - Thursday, October 18, 2012 - link

    3rd Reply
  • CaptainDoug - Tuesday, October 23, 2012 - link

    4th, Reply
  • solipsism - Tuesday, October 09, 2012 - link

    Of course a company that releases one device per product category per year as well as one with the greatest mindshare is going to have more articles.

    But what happens when you add up all Samsung phones against all Apple phones in a given year?

    What happens when you don't count the small blogs that only detail a small aspect of a secretive product but count the total words to get a better feel for the effort spent per company's market segment?

    I bet you'll find that AT spends a lot more time covering Samsung's phones than Apple's.
    Reply
  • Spunjji - Thursday, October 18, 2012 - link

    This. I generally trust their editorial, but the focus on Apple prevails. One just has to read accordingly. Reply

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