The Haswell Front End

Conroe was a very wide machine. It brought us the first 4-wide front end of any x86 micro-architecture, meaning it could fetch and decode up to 4 instructions in parallel. We've seen improvements to the front end since Conroe, but the overall machine width hasn't changed - even with Haswell.

Haswell leaves the overall pipeline untouched. It's still the same 14 - 19 stage pipeline that we saw with Sandy Bridge depending on whether or not the instruction is found in the uop cache (which happens around 80% of the time). L1/L2 cache latencies are unchanged as well. Since Nehalem, Intel's Core micro-architectures have supported execution of two instruction threads per core to improve execution hardware utilization. Haswell also supports 2-way SMT/Hyper Threading.

The front end remains 4-wide, although Haswell features a better branch predictor and hardware prefetcher so we'll see better efficiency. Since the pipeline depth hasn't increased but overall branch prediction accuracy is up we'll see a positive impact on overall IPC (instructions executed per clock). Haswell is also more aggressive on the speculative memory access side.

The image below is a crude representation I put together of the Haswell front end compared to the two previous tocks. If you click the buttons below you'll toggle between Haswell, Sandy Bridge and Nehalem diagrams, with major changes highlighted.


In short, there aren't many major, high-level changes to see here. Instructions are fetched at the top, sent through a bunch of steps before getting to the decoders where they're converted from macro-ops (x86 instructions) to an internally understood format known to Intel as micro-ops (or µops). The instruction fetcher can grab 4 - 5 x86 instructions at a time, and the decoders can output up to 4 micro-ops per clock.

Sandy Bridge introduced the 1.5K µop cache that caches decoded micro-ops. When future instruction fetch requests are made, if the instructions are contained within the µop cache everything north of the cache is powered down and the instructions are serviced from the µop cache. The decode stages are very power hungry so being able to skip them is a boon to power efficiency. There are also performance benefits as well. A hit in the µop cache reduces the effective integer pipeline to 14 stages, the same length as it was in Conroe in 2006. Haswell retains all of these benefits. Even the µop cache size remains unchanged at 1.5K micro-ops (approximately 6KB in size).

Although it's noted above as a new/changed block, the updated instruction decode queue (aka allocation queue) was actually one of the changes made to improve single threaded performance in Ivy Bridge.

The instruction decode queue (where instructions go after they've been decoded) is no longer statically partitioned between the two threads that each core can service.

The big changes in Haswell are at the back end of the pipeline, in the execution engine.

CPU Architecture Improvements: Background Prioritizing ILP
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  • 1008anan - Saturday, October 06, 2012 - link

    Haswell will sport 32 single precision or 16 double precision flops per cycle per core for its desktop and high tdp mobile skews [at least 30 watt and up].

    Can anyone speculate on how many single precision and double precision flops per cycle per core Haswell will execute for its low TDP skews? For example the less than 10 watt skews? the 15 watt skews?

    I would also be interested in learning speculation about how many execution units (or shader cores if you prefer standard nomenclature) the low TDP Haswell products will have.
    Reply
  • 1008anan - Saturday, October 06, 2012 - link

    Haswell will be able to execute 16 double precision or 32 single precision flops per clock per core for desktop and high TDP mobile skews [at least 30 watts and up].

    Can anyone speculate on how many flops per cycle per core the sub 10 watt and 15 watt Haswell skews will execute? Similarly I would be interested in hearing speculation about how many graphic execution units (shader cores) the sub 10 watt and 15 watt Haswell products will come with. Any speculation on graphics clock speed?

    Is it possible that the high end tock 22 nm Xeon server parts could have 32 double precision or 64 single precision flops per clock per core?
    Reply
  • Laststop311 - Saturday, October 06, 2012 - link

    Best explanation of haswell I've read to date. Good Job Anand. Reply
  • lmcd - Saturday, October 06, 2012 - link

    Interestingly, this might be the first chance in forever AMD has at competing with Intel. If Haswell's sole goal is to hit lower power targets, and Piledriver hits its 15% and Steamroller its 15% over that, AMD is suddenly right up with Intel's i5 series with its GPU-less chips, and upper i3-range with their APUs, which is absolutely perfect positioning: most i5 purchases are for people planning to pair with discrete graphics, while most i3 series seem to go to the PC buyer looking for low price tags.

    The one downside is that the i7 series is Intel's money-maker: the clueless people who think they're getting maximum performance but are really just feeding the binning system and buying an unbalanced PC.
    Reply
  • milkod2001 - Sunday, October 07, 2012 - link

    u got it wrong bro, Intels money maker is not i7, it's i3 and i5(low end and a bit of mainstreem)

    as for Haswell, on paper it looks too good to be true as Ivy did last year and ended up everything but impressive.

    Since Intel conroe core(2006) there actually were not any significant improvements worth mentioning.There's not much extra what todays CPUs can do and Pentium4 could not a decade ago.

    I would love to see some innovations user could really benefit from(something like reattachable,thin, light, portable, firm solar panel hooked at the back of screen or even build in as last layer into screen itself) and not that crap Intel/AMD gives us year by year.
    Reply
  • xeizo - Sunday, October 07, 2012 - link

    Anand is very right, it's everything about power savings which in effect makes smaller and more portable form factors possible!

    As for mainstream perfomance, my Linux workstation still uses a Q9450 rev. C1 from 2008 clocked at 3.2GHz and a SSD of course. That box feels in every way as snappy as my Windows-box with Sandy Bridge at 4.8GHz. Which means, I really didn't need more performance than what C2Q already gave. Of course the SB-box benchmarks much faster, about twice as fast in most things, but the point is for myself I really don't need that perfromance except for some occasional game.

    But I could use a smaller, cooler running device instead!
    Reply
  • Teknobug - Tuesday, October 16, 2012 - link

    LOL my Linux system still runs a Sempron and it's still fast. Reply
  • oomjcv - Sunday, October 07, 2012 - link

    Very interesting article, enjoyed reading it.

    Something I would like to see is a decent comparison between Intel's and AMD's plans. Many might be able to outline the basics, but a thorough article on the subject should be rather enlightening... Comparing their design philosophies, architectures, possible pitfalls and successes etc, pretty much what's been done with this article only with both companies.
    I know it might be time consuming but I imagine it could be quite a nice read.
    Reply
  • zwillx - Monday, January 21, 2013 - link

    agreed; it's difficult to find the common ground with so many different chip architectures. x86 is a big enough competition but now it's getting split wide open with ARM and BIG/litle etc etc so it's always helpful to have either more charts or real world examples lol.

    My take from this article though: Haswell still won't have the prowess to beat the GT650. I have GTX660 in my laptop w/ Optimus (TM). It works. Runs a game on HD4000 at 17 FPS. On the GTX660 I get 100+ fps, and am able to use higher anti-aliasing settings. So, clearly a 100% improvement over Ivy bridge is only putting the chip into "mediocre" category by the time its released.
    Reply
  • alexandrio - Sunday, October 07, 2012 - link

    "The bigger concern is whether or not the OEMs and ISVs will do their best to really take advantage of what Haswell offers. I know one will, but will the rest?"

    I am curious who is that one OME that will do their best to really take advantage of Haswell offers?
    Reply

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