CPU Architecture Improvements: Background

Despite all of this platform discussion, we must not forget that Haswell is the fourth tock since Intel instituted its tick-tock cadence. If you're not familiar with the terminology by now a tock is a "new" microprocessor architecture on an existing manufacturing process. In this case we're talking about Intel's 22nm 3D transistors, that first debuted with Ivy Bridge. Although Haswell is clearly SoC focused, the designs we're talking about today all use Intel's 22nm CPU process - not the 22nm SoC process that has yet to debut for Atom. It's important to not give Intel too much credit on the manufacturing front. While it has a full node advantage over the competition in the PC space, it's currently only shipping a 32nm low power SoC process. Intel may still have a more power efficient process at 32nm than its other competitors in the SoC space, but the full node advantage simply doesn't exist there yet.

Although Haswell is labeled as a new micro-architecture, it borrows heavily from those that came before it. Without going into the full details on how CPUs work I feel like we need a bit of a recap to really appreciate the changes Intel made to Haswell.

At a high level the goal of a CPU is to grab instructions from memory and execute those instructions. All of the tricks and improvements we see from one generation to the next just help to accomplish that goal faster.

The assembly line analogy for a pipelined microprocessor is over used but that's because it is quite accurate. Rather than seeing one instruction worked on at a time, modern processors feature an assembly line of steps that breaks up the grab/execute process to allow for higher throughput.

The basic pipeline is as follows: fetch, decode, execute, commit to memory. You first fetch the next instruction from memory (there's a counter and pointer that tells the CPU where to find the next instruction). You then decode that instruction into an internally understood format (this is key to enabling backwards compatibility). Next you execute the instruction (this stage, like most here, is split up into fetching data needed by the instruction among other things). Finally you commit the results of that instruction to memory and start the process over again.

Modern CPU pipelines feature many more stages than what I've outlined here. Conroe featured a 14 stage integer pipeline, Nehalem increased that to 16 stages, while Sandy Bridge saw a shift to a 14 - 19 stage pipeline (depending on hit/miss in the decoded uop cache).

The front end is responsible for fetching and decoding instructions, while the back end deals with executing them. The division between the two halves of the CPU pipeline also separates the part of the pipeline that must execute in order from the part that can execute out of order. Instructions have to be fetched and completed in program order (can't click Print until you click File first), but they can be executed in any order possible so long as the result is correct.

Why would you want to execute instructions out of order? It turns out that many instructions are either dependent on one another (e.g. C=A+B followed by E=C+D) or they need data that's not immediately available and has to be fetched from main memory (a process that can take hundreds of cycles, or an eternity in the eyes of the processor). Being able to reorder instructions before they're executed allows the processor to keep doing work rather than just sitting around waiting.

Sidebar on Performance Modeling

Microprocessor design is one giant balancing act. You model application performance and build the best architecture you can in a given die area for those applications. Tradeoffs are inevitably made as designers are bound by power, area and schedule constraints. You do the best you can this generation and try to get the low hanging fruit next time.

Performance modeling includes current applications of value, future algorithms that you expect to matter when the chip ships as well as insight from key software developers (if Apple and Microsoft tell you that they'll be doing a lot of realistic fur rendering in 4 years, you better make sure your chip is good at what they plan on doing). Obviously you can't predict everything that will happen, so you continue to model and test as new applications and workloads emerge. You feed that data back into the design loop and it continues to influence architectures down the road.

During all of this modeling, even once a design is done, you begin to notice bottlenecks in your design in various workloads. Perhaps you notice that your L1 cache is too small for some newer workloads, or that for a bunch of popular games you're seeing a memory access pattern that your prefetchers don't do a good job of predicting. More fundamentally, maybe you notice that you're decode bound more often than you'd like - or alternatively that you need more integer ALUs or FP hardware. You take this data and feed it back to the team(s) working on future architectures.

The folks working on future architectures then prioritize the wish list and work on including what they can.

Other Power Savings & The Fourth Haswell The Haswell Front End
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  • 1008anan - Saturday, October 06, 2012 - link

    Haswell will sport 32 single precision or 16 double precision flops per cycle per core for its desktop and high tdp mobile skews [at least 30 watt and up].

    Can anyone speculate on how many single precision and double precision flops per cycle per core Haswell will execute for its low TDP skews? For example the less than 10 watt skews? the 15 watt skews?

    I would also be interested in learning speculation about how many execution units (or shader cores if you prefer standard nomenclature) the low TDP Haswell products will have.
    Reply
  • 1008anan - Saturday, October 06, 2012 - link

    Haswell will be able to execute 16 double precision or 32 single precision flops per clock per core for desktop and high TDP mobile skews [at least 30 watts and up].

    Can anyone speculate on how many flops per cycle per core the sub 10 watt and 15 watt Haswell skews will execute? Similarly I would be interested in hearing speculation about how many graphic execution units (shader cores) the sub 10 watt and 15 watt Haswell products will come with. Any speculation on graphics clock speed?

    Is it possible that the high end tock 22 nm Xeon server parts could have 32 double precision or 64 single precision flops per clock per core?
    Reply
  • Laststop311 - Saturday, October 06, 2012 - link

    Best explanation of haswell I've read to date. Good Job Anand. Reply
  • lmcd - Saturday, October 06, 2012 - link

    Interestingly, this might be the first chance in forever AMD has at competing with Intel. If Haswell's sole goal is to hit lower power targets, and Piledriver hits its 15% and Steamroller its 15% over that, AMD is suddenly right up with Intel's i5 series with its GPU-less chips, and upper i3-range with their APUs, which is absolutely perfect positioning: most i5 purchases are for people planning to pair with discrete graphics, while most i3 series seem to go to the PC buyer looking for low price tags.

    The one downside is that the i7 series is Intel's money-maker: the clueless people who think they're getting maximum performance but are really just feeding the binning system and buying an unbalanced PC.
    Reply
  • milkod2001 - Sunday, October 07, 2012 - link

    u got it wrong bro, Intels money maker is not i7, it's i3 and i5(low end and a bit of mainstreem)

    as for Haswell, on paper it looks too good to be true as Ivy did last year and ended up everything but impressive.

    Since Intel conroe core(2006) there actually were not any significant improvements worth mentioning.There's not much extra what todays CPUs can do and Pentium4 could not a decade ago.

    I would love to see some innovations user could really benefit from(something like reattachable,thin, light, portable, firm solar panel hooked at the back of screen or even build in as last layer into screen itself) and not that crap Intel/AMD gives us year by year.
    Reply
  • xeizo - Sunday, October 07, 2012 - link

    Anand is very right, it's everything about power savings which in effect makes smaller and more portable form factors possible!

    As for mainstream perfomance, my Linux workstation still uses a Q9450 rev. C1 from 2008 clocked at 3.2GHz and a SSD of course. That box feels in every way as snappy as my Windows-box with Sandy Bridge at 4.8GHz. Which means, I really didn't need more performance than what C2Q already gave. Of course the SB-box benchmarks much faster, about twice as fast in most things, but the point is for myself I really don't need that perfromance except for some occasional game.

    But I could use a smaller, cooler running device instead!
    Reply
  • Teknobug - Tuesday, October 16, 2012 - link

    LOL my Linux system still runs a Sempron and it's still fast. Reply
  • oomjcv - Sunday, October 07, 2012 - link

    Very interesting article, enjoyed reading it.

    Something I would like to see is a decent comparison between Intel's and AMD's plans. Many might be able to outline the basics, but a thorough article on the subject should be rather enlightening... Comparing their design philosophies, architectures, possible pitfalls and successes etc, pretty much what's been done with this article only with both companies.
    I know it might be time consuming but I imagine it could be quite a nice read.
    Reply
  • zwillx - Monday, January 21, 2013 - link

    agreed; it's difficult to find the common ground with so many different chip architectures. x86 is a big enough competition but now it's getting split wide open with ARM and BIG/litle etc etc so it's always helpful to have either more charts or real world examples lol.

    My take from this article though: Haswell still won't have the prowess to beat the GT650. I have GTX660 in my laptop w/ Optimus (TM). It works. Runs a game on HD4000 at 17 FPS. On the GTX660 I get 100+ fps, and am able to use higher anti-aliasing settings. So, clearly a 100% improvement over Ivy bridge is only putting the chip into "mediocre" category by the time its released.
    Reply
  • alexandrio - Sunday, October 07, 2012 - link

    "The bigger concern is whether or not the OEMs and ISVs will do their best to really take advantage of what Haswell offers. I know one will, but will the rest?"

    I am curious who is that one OME that will do their best to really take advantage of Haswell offers?
    Reply

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