MIPS Technologies Updates Processor IP Lineup with Aptiv Seriesby Ganesh T S on May 10, 2012 8:55 AM EST
The interAptiv family brings multithreading to the table, something which ARM hasn't started implementing yet. As our Lava Xolo smartphone revealed, implementing simultaneous multi-threading is highly beneficial for performance, particularly in current day workloads.
MIPS claims that 3 interAptiv cores deliver performance similar to / slightly exceeding what could be obtained from 2x Cortex-A9 / 3x Cortex-A5 cores with the same silicon area. Of course, CoreMark numbers heavily favor the interAptiv cores.
In the interAptiv family, the CPU execution pipeline is shared by multiple threads, which allows the mitigation of the performance impact of memory access latencies. Since interAptiv is targeted towards real time workloads, a hardware scheduler enables a better QoS.
MIPS terms the threads as VPEs (virtual processing elements). The pipeline itself is 9 stages long and is in-order. An optional multi-threaded IEEE 754 FPU can be added if necessary. DSP ASE is available, as is EVA (similar to the proAptiv family). The CPS used with the multi-core interAptiv family has the same features as that used by the proAptiv.
Compared to the proAptiv, the interAptiv core architecture allows for core clock shutdown during outstanding bus requests, intelligent way selection in the L1 instruction cache and 32-bit L1 data cache access as options for power reduction. [ Update: Intelligent way selection in the L1 instruction cache is also available in the proAptiv family ]
In the TSMC 40nm G process, the interAptiv family members can run at up to 1 GHz for applications involving multi-threading with QoS and at up to 1.2 GHz for multi-threading without QoS. If DSP ASE is not desired, implementations can run at up to 1.5 GHz for networking applications. [ Update: The quoted frequency numbers are 'sweet spots' in terms of power consumption and other application specific requirements. As mentioned in the previous section, the frequency of operation can be scaled depending on customer requirements and is not related to the presence of absence of DSP ASE / QoS ]
The microAptiv architecture is a superset of the M14K/c cores with microMIPS code compression support. With integrated DSP ASE, signal processing comes in at a lower cost. There are options to implement without caches / MMUs depending on the application.
This 5 stage pipeline architecture can run at up to 400 MHz in a 65nm LP process. MIPS also presented a side-by-side comparison of the Cortex-M4 and the microAptiv family:
Obviously, the extra features don't come without an area penalty. In a 90nm LP process, Cortex-M4 has a floorplanned area of 0.17 mm2 compared to the 0.42 mm2 of the microAptiv MCU (cacheless version). [ Update: MIPS claims that the area numbers are not apples-to-apples comparison. Under similar implementation conditions in 90LP - read, area optimized - MIPS expects the microAptiv family to have only 0.01 mm2 extra area. Our data is from ARM's Cortex-M4 specifications. We agree it is difficult to compare the area requirements, but readers should note that there is no free lunch when it comes to feature set vs. die area ]