The proAptiv family of processors can contain 1 to 6 proAptiv cores, each of which implements in about half the size of a standard Cortex-A15 core. This is not entirely impossible, given that some people in the industry feel that ARM's Cortex-A15 implementation takes up too much area for the advertised performance. However, it is likely that the NEON engine is being accounted for in the Cortex-A15 area while the proAptiv implementation doesn't take into account the 32 bit SIMD engine (DSP ASE). [ Update: MIPS clarified that the DSP ASE is not a configurable block and is included in the quoted area. The precise area numbers for ARM are estimates only, since ARM has published no concrete specifications for the Cortex-A15. MIPS also attempted to remove the estimated area for NEON, with the desire to achieve as close to an “apples to apples” comparison in area as possible].

The proAptiv core is a superscalar out-of-order CPU with quad instruction fetch and fused triple dispatch. In the absence of any dependencies, the CPU can issue up to four integer and two floating point operations. Multi-level TLBs and branch target buffers / sophisticated branch prediction aid in getting more than 60% better performance over the previous generation 1074K series. The FPU is dual issue and runs at the same speed as the CPU.

The proAptiv and interAptiv families implement EVA (Extended Virtual Addressing) in order to better utilize the available address space. Similar to the Cortex-A15, the IP includes a coherence manager and an integrated L2 cache controller with ECC support. While Cortex-A15 supports up to 32 cores, the proAptiv family supports up to 6. An interesting aspect of the Coherent Processing System (CPS) is the presence of a cluster power controller which does clock gating per core (common in other multi-core CPUs also) and voltage domain / gating per core. The latter has interesting applications in scenarios similar to ARM's big:LITTLE architecture. Instead of tying up a big core such as the A15 with a smaller one like the A7, MIPS suggests that licensees could implement a multi-core proAptiv system with some cores running at much lower frequencies / lower voltage to save upon power (since the proAptiv cores are already small compared to the A15 core).

Architecture Comparison
  proAptiv ARM Cortex A9 Qualcomm Krait ARM Cortex A15
Decode 3-wide 2-wide 3-wide 3-wide
Pipeline Depth 13 stages 8 stages 11 stages 15 stages
Out of Order Execution Y Y Y Y
Pipelined FPU Y Y Y Y
SIMD / Media Processing Engine DSP ASE (32-bit wide) Optional MPE (64-bit wide) Y (128-bit wide) Optional MPE (128-bit wide)
Process Technology 40nm / 28nm 40nm / 32nm 28nm 28nm
Typical Clock Speeds 1.2GHz* 1.2GHz 1.5GHz 2.5GHz

While ARM expects the A15 to reach up to 2.5 GHz in the HP/G processes, MIPS only expects up to 1.5 GHz. That said, embedded applications using the proAptiv are likely to be power sensitive, and while peak performance of the A15 is likely to be much better than the proAptiv family, MIPS can tout the smaller size for equivalent performance as an advantage.

*Update: MIPS supplied detailed feedback on our architecture comparison, and I will leave it here for readers to take note:

  • MIPS and ARM provide synthesizable IP. As such, these technologies can be implemented in any process geometry and node, with standard cells and memories. At that point, it all comes down to what target a customer shoots for, what physical IP libraries and memories they use, and other implemetation specific aspects.
  • MIPS at 1.2 GHz is using readily available using TSMC's 12 track SVt libraries and representing worst case silicon corner results with production margins. MIPS projects that using more aggressive implementation techniques and typical corner silicon, proAptiv implementations can reach 2.0-2.5 GHz (similar to the Cortex-A15) [ Editor's Note: The conditions under which the Cortex -A15 reaches 2.5 GHz are unclear ]

 


 

Introduction interAptiv and microAptiv Architectures
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  • CrankUpThePowerIgor - Thursday, May 10, 2012 - link

    We have 32 bit cores?

    Phones need 64 bit as much as they need 4 cores, but I'm sure it would sell ;)
    Reply
  • jjj - Thursday, May 10, 2012 - link

    You keep mentioning die area but never list some actual numbers (or maybe i missed those?). Die are wise it is amusing that they only compare to A15 .Since it seems that it can't clock as high as A15 it's not a fair comparison.The 2 don't target the same markets anyway so w/e.
    The lower clocked core(s) solution sounds way too much like Nvidia's 4+1 ,wonder if they'll have anything to say about that.

    "it looks likely that the architecture of choice in the mobile / tablet space will become a two way shootout between ARM and x86"
    Unless China decides to go with it's own ISA and then things will get a bit more complicated.
    Reply
  • bji - Thursday, May 10, 2012 - link

    That is a terrible marketing name. Reply
  • bji - Thursday, May 10, 2012 - link

    Am I really reading that right? Are those memory controllers really that small? Sounds barely visible to the naked eye. Reply
  • ganeshts - Thursday, May 10, 2012 - link

    Yes, they are really small. Usually, there are some peripherals around them on the die, and then, there is the packaging which makes it visible to the eye :) Reply
  • metafor - Thursday, May 10, 2012 - link

    It should be noted that Krait is on the 28LP node currently and that corresponds to its frequency of 1.5GHz. ARM's A15 numbers on 28LP are around ~2GHz (OMAP 5430 being the primary example). Reply
  • ganeshts - Thursday, May 10, 2012 - link

    We can't have too many inferences from the frequency of operation.

    With appropriate choice of libraries, usage of low Vt cells etc., Qualcomm could have probably gotten Krait to run at 2 GHz had they wished. It probably means that Qualcomm is satisfied with 1.5 GHz for their target market. ARM's A15 numbers will vary widely, and the OMAP 5430 is just one case..

    We should actually compare operating frequency with the same set of libraries / same process node / same operating corner, but different vendors quote different circumstances.. So, it is not easy to make an apples-to-apples comparison.
    Reply
  • Daniel Egger - Thursday, May 10, 2012 - link

    I'm really not sure you're all getting the point here with all the ARM comparison. MIPS is not even trying (at least not hard) to get into the smartphone game. MIPS is a really strong player in the consumer grade network equipment market -- think WLAN APs and routers, DSL Modems, Mifis, etc.. There's almost no ARM or x86 anywhere to be found but since networking speeds are ever increasing an architecture update is sorely needed!

    You can compare MIPS and ARM and x86 (and if you're serious about it you'd also include Freescale) as much as you'd like but the matter of fact is: Each of these architecture has at least one weak spot that disqualifies it for some market segments:
    - Most ARM based processors have lousy I/O possibilities (crappy or no network, no PCIe)
    - Most MIPS implementations do not have powerful GPUs and CPU performance is not the best
    - x86 needs too many external components and it is effectively only available from one vendor and non-synthesizable
    - Freescale (PPC) implementations also do not have powerful GPUs, are too power hungry and far too expensive for most uses
    Reply
  • ganeshts - Thursday, May 10, 2012 - link

    Oh! MIPS is definitely trying to get a toehold in the smartphone market. In fact, I looked at a few of their smartphones in their HQ (all being sold in China).

    The drawbacks you indicate are not a problem with the processor IP. Rather, it is the SoC vendor's choice on what peripheral IPs are integrated along with the processor.
    Reply
  • Penti - Thursday, May 10, 2012 - link

    Naw they are not really trying, the Ingenic chip the Chinese devices uses is a custom design by the Chinese firm Ingenic. Not CPUs designed by MIPS Technologies. Those has to compete with Chinese as well as cheap semi-local Taiwanese ARM-designs with ARM RTL-cores and embedded baseband too. Nothing much happening there. Not from Mips Tech standpoint any way. The MIPS SoCs can use the same third party synthesizeable IP GPUs, video engines as the ARM counterparts and so on. But don't expect much in the form of baseband modems on MIPS processors. Smartphones run fine with either x86, ARM or MIPS though. Android has support for them all. A few years ago there were some other architectures involved in the business too. Let's see if anybody uses MIPS Technologies IP cores to build phones first before shouting anything. We won't really have the same situation if you can't use RTL-cores at any fab and multiple vendors delivering solutions on that. It's hard to compete if there is just one vendor with their own custom designs. Freescale will continue their i.MX ARM line for phones/tablets. ARM is taking over the whole CE field including TVs, blu-ray players and so on too for that matter. Still some good MIPS-designs around though. But there are good designs of most stuff around. Tools and software certainly would draw you to ARM though. Reply

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