Google TV Goes ARM with Marvell's ARMADA 1500by Ganesh T S on January 5, 2012 8:01 AM EST
The ARMADA 1500 (88DE3100) is a media SoC with a dual core PJ4B superscalar host processor. It is targeted towards IP/Cable/Satellite STBs, premium Blu-ray players / DMAs and Google TV applications.
The following block diagram reveals the structure of the 88DE3100 SoC:
We will take a look at the I/Os first:
- A/V Inputs: Just like the CE4100, the Marvell chip also has Transport Stream inputs and support for digital inputs (plain YUV / RGB). The TS inputs are probably not of much use in Google TV applications, but I can definitely see the digital inputs being used in cases where the device needs to have a HDMI input (from a STB output) for blending / overlay.
- A/V Outputs: The SoC has a HDMI 1.4 compliant TX PHY with 1080p60 / frame and field interleaved 3D support and 12b Deep Color capability. HD audio bitstreaming and CEC support are also available. along with various combinations of component / composite / S-Video and digital audio outputs.
- Memory Interface: 32-bit DDR3 DRAM running at 800 MHz provides for 61.2 Gbps of maximum theoretical bandwidth. Up to 1 GB of DRAM is supported.
- NAND Controller: This is a 8 bit interface running at 50 MHz compliant with ONFI 1.0 specifications. Up to 2 GB of NAND Flash is supported.
- Peripherals: SATA3, USB 2.0 Host, USB 2.0 Slave, SD3.0 controller, Two Fast Ethernet (100 Mbps) ports and other miscellaneous peripherals round up the SoC features.
The PJ4B CPU core was first sampled by Marvell in October 2010. It is supposed to be compatible with Cortex-A9 and delivers similar instruction throughput per cycle. Being a custom designed architecture, it has the capability to clock at a higher rate compared to off-the-shelf Cortex-A9s. While ARM estimates that the Cortex-A9 can provide around 2.5 DMIPS/MHz/Core, Marvell claims that the PJ4B can provide up to 2.61 DMIPS/MHz/Core (take this for what it is worth).
Each PJ45B core in the 88DE3100 is supported by a 4-way 32KB I-Cache and a 8-way 32KB D-Cache. There is a common 512KB coherent L2 cache.
Unlike the previous members of the ARMADA lineup which didn't have NEON support, the 88DE3100 supports both NEON VFPU and Intel WMMX. The cores are clocked at 1.2 GHz, delivering up to 6000 DMIPS of performance. This sort of performance enables the 88DE3100 to support Flash enabled web browsers and other such key areas necessary for Google TV to shine
The vMeta video decoder supports more formats than I have ever seen on any media processing chip (Sigma and Realtek included!). The 88DE3100 provides for dual stream decode acceleration of
- H.264 High Profile @ Level 4.1, 4.2 and 5; Multiple View Coding
- VC-1 Advanced profile @ level 3, WMV9 MP@HL
- MPEG-2 MP@HL, MP@ML
- MPEG4 SP@L3, ASP@L5, DIVX-HD
- AVS 6.2
- VP6/8 SD and HD
- RV9/10 (RMVB up to 1080p)
- Low Delay Mode (progressive refresh) support for H.264 Baseline profile
The vMeta engine also supports JPEG/PNG/GIF/TIFF/BMP/Animated GIF decoding acceleration up to 50MP/s. A number of containers are also specified as being supported officially, but that is usually a matter of firmware.
Qdeo Post Processing
The Qdeo post processing engine performs per-pixel 3D noise reduction, 3D de-interlacing, scaling, natural depth expansion, intelligent color remapping and adaptive contrast enhancement. I am quite sure this would compare favorably with whatever Sigma Designs has up its sleeve in the VXP post processing engine in the SMP8910.
One of the complaints I had about the 88DE3010 (ARMADA 1000) was the absence of a 3D graphics engine. The 88DE3100 takes care of that by including the GC1000 GPU from Vivante. The GPU supports OpenGL-ES 1.1 / 2.0, something necessary for XBMC to run on the chip. The GPU itself clocks at 750 MHz (with a maximum theoretical DRAM bandwidth of 3.2 Gbps), providing for 375M vertex/S and 750M pixel/S vertex and texture rates. A separate 3D drawing and stretch BLT engine (400M pixel/S fill rate) is used in cases where the 3D engine is an overkill.
The Audio DSP is a 500 MHz superscalar processor capable of executing 4 instructions per cycle. and is complemented by a 800 MHz audio post processing engine. This allows for simultaneous decoding, post processing and downmixing of audio channels. A 500 MHz security processor takes care of multiple cryptography functions to keep the DRM believing folks happy.
The SoC itself is specified to have a maximum power consumption of 5.3W, with a recommendation to budget for up to 6.5W TDP based on system design. With this power profile, it is indeed possible to have fanless operation with a passive cooling solution.