Understanding TLC NAND
by Kristian Vättö on February 23, 2012 1:14 PM EST- Posted in
- Storage
- SSDs
- OCZ
- Indilinx Everest
- TLC
A Brief Introduction to SSDs and Flash Memory
In almost every SSD review we have published, Anand has mentioned how an SSD is the biggest performance upgrade you can make today. Why would anyone use regular hard drives then? There is one big reason: price. SSD prices are still up in the clouds when compared to hard drive prices (especially before the Thailand floods) so for many, SSDs have not been a realistic option.
Forking over $700 for a 512GB SSD sounds crazy because a 500GB hard drive can be had for less than $50. Smaller capacities like 64GB and 128GB can already be bought for around $100 and $200 respectively, but unless you have the ability to have an SSD plus hard drive combo, such a small SSD doesn't usually cut it. If you have a desktop, the SSD + HDD combo should not be a problem but many laptops only have space for one 2.5" drive (unless you are willing to mod it afterwards by replacing the optical drive). SSD prices have been dropping for years now, but if the current rate continues it will take years before a $399 Walmart PC includes a reasonable size SSD. So what can be done?
Most of the time, SSD production costs are cut by shrinking the NAND die. Shrinking the die is the same as with CPUs: you move to a smaller manufacturing process, e.g. from 34nm to 25nm. In flash memory, this means you can increase the density per die and usually the physical die size is also smaller, meaning more dies from a single wafer. A die shrink is an effective way to lower costs but moving from one process to another takes time and the initial ramp of the new flash isn't necessarily cheaper. Once the new process has matured and supply has met demand, prices start to fall.
Since die shrinks are a relatively slow way to lower SSD prices and only contribute to steady reduction of prices, anyone looking to push higher capacity SSDs into the mainstream today will need something more. Right now, that "something more" is called Triple Level Cell flash, commonly abbreviated as TLC.
Rather than shrinking the die to improve density/capacity, TLC (like MLC) increases the number of bits per cell. In our SSD Anthology article, Anand described how SLC and MLC flash work, and TLC works the same way but takes things a step further. Normally, you apply a voltage to a cell and keep increasing it until you reach a point where the result is far enough from the "off" state that you now consider the cell as being "on". This is how SLC works, storing one bit per cell. For MLC, you store two bits per cell, which means instead of two voltage states (0 and 1) you have four states (00, 01, 10, 11). TLC takes that a step further and stores three bits per cell, or eight voltage states (000, 001, 010, 011, 100, 101, 110, and 111). We will take a deeper look into voltage states and how they work in the next page.
Even though SLC, MLC and TLC operate the same way, there is one crucial difference. Lets take a look at what happens to a NAND array depending on the amount of data per cell. The image above is a NAND array with ~16 billion transistors (one transistor is required per cell), i.e. 16 gigabits (Gb). This array can be turned into either SLC, MLC, or TLC. The actual array and transistors are equivalent in all three flash types; there is no physical difference. In the case of SLC flash, only one bit of data will be stored in one cell, hence your final product has a 16Gb capacity. When you up the bits per cell to two (MLC), you get 32Gb because now you have two bits per cell and there are still 16 billion cells. Likewise, three bits per cell (TLC) yields 48Gb.
However, TLC is a horse of slightly different color in this case. Capacities usually go in powers of two (2, 4, 8, 16 and so on) and 48 is not a power of two. To get a number that is a power of two, the original NAND array is chopped down. In our example, the array must be 10.67Gb in order to be 32Gb with three bits per cell, but since that is the same capacity as an MLC die, what is the benefit? You don't get more storage per die, but the actual die is smaller because the original 16Gb array has been reduced to a 10.7Gb array. That means more dies per wafer and hence lower cost.
| Comparison of NAND Wholesale Prices | |||
| Cell Type | SLC | MLC | TLC |
| Price per GB | $3.00 | $0.90 |
$0.60 |
Prices provided by OCZ
The theoretical price advantage of TLC isn't as great as SLC versus MLC, but it's still significant. In percentage, that is over a 30% reduction. The main reason is that MLC provides twice the capacity when compared to SLC (2bits per cell versus 1bit per cell), whereas TLC provides only 50% more than MLC (3bits per cell versus 2bits per cell). In fact, the price difference between MLC and TLC is directly proportional. TLC die is 33% smaller than a similar MLC die and in the prices provided by OCZ, TLC is also 33% cheaper than MLC. In theory, SLC should follow this equation as well and be priced at $1.80/GB, but there's limited 2Xnm SLC out in the wild, making SLC significantly more expensive than MLC and TLC at this point.
The reality of the matter is a little less clear. TLC NAND today isn't all that much cheaper than MLC NAND, which has contributed to its relative absence in the consumer SSD space. There's also a lack of controller support and market interest, which contribute to the higher prices of course.
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Kristian Vättö - Saturday, February 25, 2012 - link
I just used the names that manufacturers use. If you look at e.g. Micron's part catalog (linked below), they use SLC, MLC and TLC. I agree that the naming is misleading because MLC should refer to any NAND with multiple bits per cell. TLC is sometimes called as 3-bit-per-cell MLC or just MLC-3 but the TLC name is gaining more momentum all the time.http://www.micron.com/products/nand-flash/mass-sto...
foolsgambit11 - Sunday, February 26, 2012 - link
Thanks.Taracta - Sunday, February 26, 2012 - link
Shouldn't the TLC be 64Gb? It holds twice as much information as MLC as MLC hold twice as much as SLC. Each increment in bits doubles the information stored as stated in the article, SLC 2bits stored, MLC 4bits stored and TLC 8bits (1 BYTE) stored.Taracta - Sunday, February 26, 2012 - link
You are dealing with base-2 values. Each additional bit doubles the amount of data that is stored. You even have the correct values in the begining of the article. SLC stores 2 bitsof information 0 and 1, MLC stores 4 bits of information 00, 01, 10, 11 and TLC store 8 bits (1 BYTE) of information 000, 001, 010, 011, 100, 101, 110, 111 yet further down in the article you are stating that TLC stores only a third more that of SLC. You are confusing the bit place holder with the actual information that is being stored. TLC has an additional bit place holder compared to MLC which has an additional bit place holder compared to SLC. Each bit place holder increases the storage capability by a power of two (2).Kristian Vättö - Sunday, February 26, 2012 - link
SLC stores 1-bit per cell/transistor and the value can be either 0 or 1. It cannot be 0 and 1 at the same time.MLC stores 2-bits cell. This means the value can be either 00, 01, 10, or 11. However, it can only be programmed to have one value. One MLC cell cannot store e.g. 00 and 01 at the same time. One 0 or 1 is one bit of data, i.e. 00 is two bits of data. I don't know how you are coming up with four bits, maybe you are mixing it with the voltage states (each value needs its own voltage state so when you program a cell to e.g. 00, it will be read as 00).
TLC just increases the bits per cell to three which means the possible values are 000, 001, 010, 100, 011, 110 101, and 111. Again, eight voltage states and three bits per cell.
Each additional bit per cell increases the voltage states by a power of 2 (in math terms: 2^n, where n is the amount of bits per cell). Amount of bits per cell is just n, it's not a power of two. MLC is 2*1=2, and 2 is 100% bigger than 1. TLC is 3*1=3. and 3 is 200% bigger than 1 but only 50% more than 2.
Taracta - Sunday, February 26, 2012 - link
Ok let me make it simple because I still think you are confusing yourself.SLC possible values are 0 or 1 which is equal to 2 values with is 2^1
MLC possible values are 0, 1, 10 or 11 which is equal to 4 values which is 2^2
TLC possible values are 0, 1, 10, 11, 100, 101, 110 or 111 which is equal to 8 values which is 2^3
Therefore each TLC which stores 8 values (3bits) which is twice that of a MLC which stores 4 values (2bits) which is twice that of a SLC which stores 2 values (1bit)
Is this right?
KitsuneKnight - Sunday, February 26, 2012 - link
He's not confusing himself, you're confused about binary numbers and bits."Therefore each TLC which stores 8 values (3bits) which is twice that of a MLC which stores 4 values (2bits) which is twice that of a SLC which stores 2 values (1bit)"
Don't confuse the amount of bits of storage, with the maximum value it can hold.
Since you seem to be getting confused with binary numbers, lets work with decimals numbers for a bit.
Lets say an 'SLC' can represent the values 0-9. An MLC can represent the values 0-9, 0-9 or 00-99 (that's two sets of 0-9 next to each other!). A TLC can represent the values 0-9,0-9,0-9 or 000-999. It should be patently obvious that an TLC doesn't have 100 times the capcity of an SLC cell! A /single one/ can hold a VALUE 100 times, but, 3 SLCs next to each other could hold the same value.
A linear growth of bits results in an /exponential/ growth of the value those bits, when combined, can represent. It doesn't matter if all those bits are from a single cell, or X number of cells. How you get bits doesn't matter.
Taracta - Monday, February 27, 2012 - link
Kristian,Did some research to see where you were coming from with the data you presented.
http://cseweb.ucsd.edu/users/swanson/papers/ICNC20...
gives some insight on TLC block sizes and why is doesn't follow the actual size of a TLC cell. Basically some pages and not use in TLC block configurations. Strangely the amount of pages in a TLC block is more than double that of a MLC block!
I leave it up to you to clarify the article as it is somewhat confusing and needs some explanation of the differences between the cell, page and block sizes for TLC.
Kristian Vättö - Monday, February 27, 2012 - link
Actually, TLC block size does (or at least should) follow the bits-per-cell idea. 25nm IMFT MLC NAND brought us 8KB pages and 256 pages per block. According to your link, TLC has 384 pages per block (i.e. 3*128 which means 128 pages per bit). MLC is now using that same 128 pages per bit idea (before it was 64 pages per bit).It's possible that TLC moved to a bigger block size before MLC and SLC because that lowers the cost and ultimately TLC is all about cost. There is need for less peripheral circuits between the blocks, which makes the die smaller and hence reduces production costs.
http://www.micron.com/~/media/Documents/Products/T...
http://www.anandtech.com/show/2928
I don't know what this has to do with your original point about the article being wrong, though. Of course, I'm happy to answer any questions regarding TLC, or at least give it a try (I haven't studied NAND technology in a university so e.g. that math stuff in your link is over my head).
mdshann - Monday, March 5, 2012 - link
I haven't seen a 500 GB hard drive for anywhere near $50 in about 6 months now... where are you getting these drives? Right now the cheapest 500 GB drive on newegg.com is $84.99 and it's a bare Hitachi.