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Measuring Real-World Power Consumption, Part One

The Equal Workload (EWL) version of vApus FOS is very similar to our previous vApus Mark II "Real-world Power" test. To create a real-world “equal workload” scenario, we throttle the number of users in each VM to a point where you typically get somewhere between 20% and 80% CPU load on a modern dual CPU server. The amount of requests is the same for each system, hence "equal workload".

The CPU Load on the Opteron 6276 looked like this:

The CPU load is typically around 30-50%, with peaks up to 65%. At the end of the test, we get to a low 10%, which is ideal for the machine to boost to higher CPU clocks (Turbo) and race to idle. First we check out the response times.

vApus FOS Response times (ms)
CPU PhpBB1 PHPBB2 MySQL OLAP Zimbra
AMD Opteron 6276 134 47 3.6 44
AMD Opteron 6174 118 41 3.8 45
Intel Xeon X5670 76 27 2.2 28

ESXi and our Interlagos "Opteron" probably don't understand each other fully, given the newness of the architecture. Some extensive monitoring with ESXtop shows that the lower CPU load is spread among all the cores, and the result is that the Opteron 6276 never reaches its highest clock speed (3.2GHz). That helps make the response times significantly higher than on the Xeon, although they are acceptable. Again, the Interlagos Opteron fails to really beat the "Magny-cours" Opteron.

Our main focus of this benchmark is of course energy consumption.

vApus FOS EWL Power consumption

The Xeon consumes 25% less power, and the older Opteron about 10% less. The performance/Watt ratio of the newest Opteron looks rather bad when running on top of ESX. We shall delve into this deeper in the next several pages.

Virtualization Performance: Linux VMs on ESXi Virtualization Performance: ESX + Windows
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  • JohanAnandtech - Thursday, November 17, 2011 - link


    1) Niagara is NOT a CMT. It is interleaved multipthreading with SMT on top.

    I haven't studied the latest Niagaras but the T1 was a fine grained mult-threaded CPU. It switched like a gatling gun between threads, and could not execute two threads at the same time.
    Reply
  • Penti - Thursday, November 17, 2011 - link

    SPARC T2 and onwards has additional ALU/AGU resources for a half physical two thread (four logically) solution per core with shared scheduler/pipeline if I remember correctly. That's not when CMT entered the picture according to SUN and Sun engineers any way. They regard the T1 as CMT as it's chip level. It's not just a CMP-chip any how. SMT is just running multiple threads on the cpus, CMP is working the same as SMP on separate sockets. It is not the same as AMDs solution however. Reply
  • Phylyp - Tuesday, November 15, 2011 - link

    Firstly, this was a very good article, with a lot of information, especially the bits about the differences between server and desktop workloads.

    Secondly, it does seem that you need to tune either the software (power management settings) or the chip (CMT) to get the best results from the processor. So, what advise is AMD offering its customers in terms of this tuning? I wouldn't want to pony up hundreds of dollars to have to then search the web for little titbits like switching off CMT in certain cases, or enabling High-performance power management.

    Thirdly, why is the BIOS reporting 32 MB of L2 cache instead of 8 MB?
    Reply
  • mino - Wednesday, November 16, 2011 - link

    No need for tuning - turbo is OS-independent (unless OS power management explicitly disables it aka Windows).
    Just disable the power management on the OS level (= high performance fro Windows) and you are good to go.
    Reply
  • JohanAnandtech - Thursday, November 17, 2011 - link

    The BIOS is simply wrong. It should have read 16 MB (2 orochi dies of 8 MB L3) Reply
  • gamoniac - Tuesday, November 15, 2011 - link

    Thanks, Johan. I run HyperV on Windows Server 2008 R2 SP1 on Phonem II X6 (my workstation) and have noticed the same CPU issue. I previously fixed it by disabling AMD's Cool'n'Quiet BIOS setting. After switching to high performance increase my overall power usage by 9 watts but corrected the CPU capping issue you mentioned.

    Yet another excellent article from AnandTech. Well done. This is how I don't mind spending 1 hour of my precious evening time.
    Reply
  • mczak - Tuesday, November 15, 2011 - link

    L1 data and instruction cache are swapped (instruction is 8x64kB 2-way data is 16x16kB 4-way)
    L2 is 8x2MB 16-way
    Reply
  • JohanAnandtech - Thursday, November 17, 2011 - link

    fixed. My apologies. Reply
  • hechacker1 - Tuesday, November 15, 2011 - link

    Curious if those syscalls for virtualization were improved at all. I remember Intel touting they improved the latency each generation.

    http://www.anandtech.com/show/2480/9

    I'm guessing it's worse considering the increased general cache latency? I'm not sure how the latency, or syscall, is related if at all.

    Just curious as when I do lots of compiling in a guest VM (Gentoo doing lots of checking of packages and hardware capabilities each compile) it tends to spend the majority of time in the kernel context.
    Reply
  • hechacker1 - Tuesday, November 15, 2011 - link

    Just also wanted to add: Before I had a VT-x enabled chip, it was unbearably slow to compile software in a guest VM. I remember measuring latencies of seconds for some operations.

    After getting an i7 920 with VT-x, it considerably improved, and most operations are in the hundred or so millisecond range (measured with latencytop).

    I'm not sure how the latests chips fare.
    Reply

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