ARM & Cadence Tape Out 20nm Cortex A15 Test Chip
by Anand Lal Shimpi on October 18, 2011 10:30 AM EST- Posted in
- CPUs
- Arm
- Cortex A15
- 20nm
- SoCs
Although we won't see the first ARM Cortex A15 based designs until the second half of next year, and even then only on 28/32nm processes, ARM and design tools supplier Cadence have announced the first tape-out of a 20nm Cortex A15 based test chip. Tape out signals the end of an overall design phase and the release of the design to the foundry for manufacturing. The Cortex A15 is expected to be a significant step forward for ARM, bringing its designs further up the chain into the low-end x86 notebook market in addition to current smartphone/tablet targets. Cortex A15 based designs will also go head to head with Qualcomm's Krait based Snapdragon S4.
The test chip will be fabbed at TSMC on it's next-generation 20nm process, a full node reduction (~50% transistor scaling) over its 28nm process. With the first 28nm ARM based products due out from TSMC in 2012, this 20nm tape-out announcement is an important milestone but we're still around two years away from productization.
Source: Cadence
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Hector2 - Wednesday, October 19, 2011 - link
No. There's no die at all. They never went that far with this tapeout."Tapeout" is a carryover from the '80s and '90s when reel-to-reel magnetic tapes were used to store the completed design. The finished CAD files contain the artwork for each mask layer. After "tapeout", this mag tape gets sent to the mask shop to generate the individual masks which define each process layer (metal 1, metal 2, via, diffusion, etc).
In the real world, when you really do make wafers, after tapeout, the mask shop generates the masks (also called reticles) from the "tape". Today there's no tape, of course, but the term is still used. The CAD design is simply stored on a hard drive. Using the individual masks at the lithography step, wafers being built up get each level of the circuit created as the wafers go through the fabrication process. Since there's no 20nm process, this 20nm "tapeout" was never used and was never sent to create the mask set --- which today costs LOTS of money to make
Hector2 - Thursday, October 20, 2011 - link
Just in the news today -- "TSMC reiterated that a pilot line at Fab 12 Phase VI starting with 20nm process technology, would be timed around 2013/2014, and a production line set for Fab 15 following around 2015/2016"So much for a 20nm ARM processor soon. Another reminder that "tapeout", after all, is just a tapeout, nothing more, nothing less. There's no actual silicon involved.
shbdf - Friday, November 4, 2011 - link
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