Earlier this week Intel sent us a cryptic message:

I wanted to invite you to an Intel press conference on Wednesday May 4th at 9:30am Pacific time. Intel will be making its most significant technology announcement of the year. No further details will be provided in advance. The event will be held in San Francisco so for those of you are local in the SF Bay Area please attend in person if you like. It will also webcasted live. Tune-in details and logistics are below. Please let me know if you can attend.

A while ago Intel decided that a nice way to drive up its stock price would be to behave more like Apple, keeping major announcements under wraps and introducing them on its own terms to hopefully build up anticipation and excitement for Intel's announcements. You've seen examples of this with how closely Intel held Sandy Bridge's architectural details before its presentation at IDF, and how little we knew about Quick Sync (Sandy Bridge's hardware video transcoder) until Intel decided it was time to talk about it.

Apple can get away with it since most of its products are tangible, consumer facing devices. Intel's technologies are arguably even more important, but they're just not as easy for the general populace to get excited about. Today's announcement is the perfect example of just that.

Earlier today Intel announced that its 22nm process would not use conventional planar transistors but rather be the first time Intel is using 3D Tri-Gate transistors. This is a huge announcement that fuels Intel's leadership in the mobile/desktop/server CPU space and makes it a lot more attractive in the SoC space, let's understand why.

The Transistor

Here's a simple diagram of a standard 32nm planar transistor, exactly what you'd find in a Sandy Bridge CPU:


I
mage Courtesy Intel Corporation

I spent a couple of semesters as a computer engineering student a few years ago studying how these things work. There's a lot of math and it's not fun to do over and over again so we'll ignore all of that for now. The basics are thankfully much more fun to understand.

 


Image Courtesy Intel Corporation

The goal of a transistor is to act as a very high speed electrical switch. When on, current flows from the transistor's source to the drain. When off, current stops. The inversion layer (blue line above) is where the current flow actually happens.

Ideally a transistor needs to do three things:

1) Allow as much current to flow when it's on (active current)
2) Allow as little current to flow when it's off (leakage current)
3) Switch between on and off states as quickly as possible (performance)

The first item impacts how much power your CPU uses when it's actively doing work, the second impacts how much power it draws when idle and the third influences clock speed.

In conventional planar transistors it turns out that voltage in the silicon substrate impacts leakage current in a negative way. Fully depleted SOI (silicon on insulator) is an option to combating this effect.

The smaller you make the transistors, the more difficult it is to make advancements in all three of these areas all while increasing transistor density. After all not only do you have to worry about keeping power under control, but the whole point to shrinking transistor dimensions is to cram more of them into the same physical die area, thus paving the way for better performance (more cores, larger caches, higher performance structures, more integration).

The 3D Tri-Gate Transistor

A 3D Tri-Gate transistor looks a lot like the planar transistor but with one fundamental change. Instead of having a planar inversion layer (where electrical current actually flows), Intel's 3D Tri-Gate transistor creates a three-sided silicon fin that the gate wraps around, creating an inversion layer with a much larger surface area.

 


I
mage Courtesy Intel Corporation

There are five outcomes of this move:

1) The gate now exerts far more control over the flow of current through the transistor.
2) Silicon substrate voltage no longer impacts current when the transistor is off.
3) Thanks to larger inversion layer area, more current can flow when the transistor is on.
4) Transistor density isn't negatively impacted.
5) You can vary the number of fins to increase drive strength and performance.

The first two points in the list result in lower leakage current. When Intel's 22nm 3D Tri-Gate transistors are off, they'll burn less power than a hypothetical planar 22nm process.

 


Image Courtesy Intel Corporation

The third point is particularly exciting because it allows for better transistor performance as well as lower overall power. The benefits are staggering:


Image Courtesy Intel Corporation

At the same switching speed, Intel's 22nm 3D Tri-Gate transistors can run at 75 - 80% of the operating voltage of Intel's 32nm transistors. This results in lower active power at the same frequency, or the same active power at a higher performance level. Intel claims that the reduction in active power can be more than 50% compared to its 32nm process.


Image Courtesy Intel Corporation

At lower voltages Intel is claiming a 37% increase in performance vs. its 32nm process and an 18% increase in performance at 1V. High end desktop and mobile parts fall into the latter category. Ivy Bridge is likely to see gains on the order of 18% vs. Sandy Bridge, however Intel may put those gains to use by reducing overall power consumption of the chip as well as pushing for higher frequencies. The other end of that curve is really for the ultra mobile chips, this should mean big news for the 22nm Atom which I'm guessing we'll see around 2013.


Image Courtesy Intel Corporation

You'll note that the move to 3D Tri-Gate transistors doesn't negatively impact transistor density. In fact Intel is claiming a 2x density improvement from 32nm to 22nm (you can fit roughly twice as many transistors in the same die area at 22nm as you could on Intel's 32nm process).

 


Image Courtesy Intel Corporation

It's also possible to vary the number of fins to impact drive strength and performance, allowing Intel to more finely tune/target its 22nm process to various products.

The impact on manufacturing cost is also minimal. Compared to a hypothetical Intel 22nm planar process, the 3D Tri-Gate process should only cost another 2 - 3%


Image Courtesy Intel Corporation

All 22nm products from Intel will use its 3D Tri-Gate transistors.

What Does This Mean

Intel's Ivy Bridge is currently scheduled for a debut in the first half of 2012. Intel is purposefully being vague about the release quarter as Sandy Bridge is doing well and isn't facing much competition at the high end at least.

The impact of Intel's 22nm 3D Tri-Gate transistors on high end x86 CPUs will be significant. Intel isn't expecting its competitors to move to a similar technology until 14nm. The increases in switching speed at the same voltage could allow Intel to finally hit or exceed that magical 4GHz barrier in a stock CPU. I suspect Intel will likely use the gains to deliver lower power CPUs however there's always the possibility of some very fast Extreme Edition parts.


Image Courtesy Intel Corporation.

The bigger story here actually has to do with Atom. The biggest gains Intel is showing are at very low voltages, exactly what will benefit ultra mobile SoCs. Atom has had a tough time getting into smartphones and while we may see limited success at 32nm, the real future is what happens at 22nm. Atom is due for a new microprocessor architecture in 2012, if Intel goes the risky route and combines it with its 22nm process it could have a knockout on its hands.

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  • ssj4Gogeta - Thursday, May 05, 2011 - link

    Can you even relate cache size to speed across multiple architectures?

    Get an SSD and use it as the system drive.
    Reply
  • Azethoth - Thursday, May 05, 2011 - link

    400 tabs eh. When you start up your browser, how many hours does it take to fetch fresh pages from the internets? After they are ready for display, how many days does it take you to cycle through all tabs and see whats new? Do you lose track of where you are and have to restart? Inquiring minds want to know. Reply
  • smut - Thursday, May 05, 2011 - link

    400 tabs? WTF, elaborate please! Reply
  • chukked - Friday, May 06, 2011 - link

    multiple portable opera browser sessions, each for different subject and having a lots of tabs, just see it as each one serving as a research, collection workspace.

    right now this anandtech session alone has 57 tabs from 3-jan-2011 covering intel i7

    no it does not take eternity to load, they all open simultaneously, i have tweaked cache setting of opera and firefox both but firefox only one session runs unlike opera so i mostly use opera.

    anyway i use bartab plugin in firefox which prevent opera from loading any tab except the one having focus, so loading is not an issue. and yes it has more then 400 tabs even after i splitted it in to separate folders one is tech and another is science and energy (cold fusion is exotic).

    a big cache alone is capable to improve the system response time by a big factor even your ssd can not do anything moreover it prevents system hang and windows crash altogether when you are switching programs to programs very quickly.
    Reply
  • banvetor - Thursday, May 05, 2011 - link

    One point that I didn't see anyone talking about is the apparent change in the CMOS design paradigm that smaller technologies mean smaller transistor length (L).

    From the slides available at Intel website (of which some are shown here), it seems that in this new 22nm 3D transistor, the technology resolution corresponds to the gate width (W), and not length...

    It's interesting to think how this change will affect the chip design...
    Reply
  • Shadowmaster625 - Thursday, May 05, 2011 - link

    This is probably why intel's stock price jumped 20% a couple weeks ago. So now we know how long the banksters have the inside info. Anyway it is just a pump and dump scheme. If you look at the "Transistor Gate Delay" chart carefully, you will notice that each new process node yields a similar improvement. If you actually compare regular planar gates at 32nm vs regular planar gates at 45nm, you see the same ~25% improvement. In reality this particular innovation (the waffling) is only good for a few percent. So are we really to believe that a bit of waffling is the best Intel can do this year? If so, they are in trouble. I think their marketing department is doing even more waffling than their engineers. Reply
  • marc1000 - Thursday, May 05, 2011 - link

    second! Reply
  • fic2 - Thursday, May 05, 2011 - link

    Intel CEO made an announcement a couple of weeks ago that their 22nm tech would be revolutionary but wouldn't say anything more than that.

    If this is Intel "waffling" wtf are other companies doing? Intel is way ahead of everybody else. This puts them further ahead. If Intel is in trouble all the other companies are just walking dead then.
    Reply
  • albundy12345 - Thursday, May 05, 2011 - link

    Or, maybe their stock price jumped because they pocketed 1 billion dollars a month for the last half a year. Reply
  • ironargonaut - Friday, May 06, 2011 - link

    You have totally disregarded the power savings mentioned in the article and elsewhere. The more power you save the higher you can make the frequency which increase the performance. So in effect pwr savings equals performance boost.

    Remember when Intel reduced the leakage current significantly? Remember the raging success of that part?
    Reply

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