The Anatomy of an SSD

Let’s meet Mr. N-channel MOSFET again:

Say Hello

This is the building block of NAND-flash; one transistor is required per cell. A single NAND-flash cell can either store one or two bits of data. If it stores one, then it’s called a Single Level Cell (SLC) flash and if it stores two then it’s a Multi Level Cell (MLC) flash. Both are physically made the same way; in fact there’s nothing that separates MLC from SLC flash, it’s just a matter of how the data is stored in and read from the cell.


SLC flash (left) vs. MLC flash (right)

Flash is read from and written to in a guess-and-test fashion. You apply a voltage to the cell and check to see how it responds. You keep increasing the voltage until you get a result.

  SLC NAND flash MLC NAND flash
Random Read 25 µs 50 µs
Erase 2ms per block 2ms per block
Programming 250 µs 900 µs

 

With four voltage levels to check, MLC flash takes around 3x longer to write to as SLC. On the flip side you get twice the capacity at the same cost. Because of this distinction, and the fact that even MLC flash is more than fast enough for a SSD, you’ll only see MLC used for desktop SSDs while SLC is used for enterprise level server SSDs.


Cells are strung together in arrays as depicted in the image to the right

So a single cell stores either one or two bits of data, but where do we go from there? Groups of cells are organized into pages, the smallest structure that’s readable/writable in a SSD. Today 4KB pages are standard on SSDs.

Pages are grouped together into blocks; today it’s common to have 128 pages in a block (512KB in a block). A block is the smallest structure that can be erased in a NAND-flash device. So while you can read from and write to a page, you can only erase a block (128 pages at a time). This is where many of the SSD’s problems stem from, I’ll repeat this again later because it’s one of the most important parts of understanding SSDs.


Arrays of cells are grouped into a page, arrays of pages are grouped into blocks

Blocks are then grouped into planes, and you’ll find multiple planes on a single NAND-flash die.

The combining doesn’t stop there; you can usually find either one, two or four die per package. While you’ll see a single NAND-flash IC, there may actually be two or four die in that package. You can also stack multiple ICs on top of each other to minimize board real estate usage.

 

Hey, There’s an Elephant in the Room Strength in Numbers, What makes SSDs Fast
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    I need to run HDDErase on an X25-M. No matter what bootable CD or flash drive I create, HDDErase does not see either of my SATA hard drives. I already disabled AHCI in BIOS. Also, I am using version 3.3. I know that 4.0 does not work with the X25-M.

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  • gallde - Thursday, June 11, 2009 - link

    You point out that TRIM will only work on deletions, not on overwrites. But, couldn't a smart controller look at blocks that have a majority of invalid pages and "trim" them as well, recovering clean pages as a background process? Reply
  • forsunny - Thursday, August 13, 2009 - link

    Why not just make the SSDs capable of individual page erases instead of blocks? Problem solved. Reply

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