Gigabyte GA-EP45-UD3P - P45 at its Finestby Gary Key on February 3, 2009 12:15 AM EST
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The GA-EP45-UD3P is based on the Intel P45/ICH10R chipset combination. The P45 is manufactured on a 65nm process, which makes it not only smaller but more energy efficient than 90nm chipsets like the X48. It typically runs much cooler than the X48 and P35. Officially, the P45 does not support the 1600Mhz front-side bus used on the Core 2 Extreme QX9770 quad-core processor. However, just about all motherboard manufacturers are unofficially supporting 1600FSB.
The P45 supports either DDR2 or DDR3 memory. Once again, official support is limited to JEDEC approved memory speeds up to DDR2-800 or DDR3-1066. Unofficial memory support by the manufactures is available for speeds up to DDR2-1366 and DDR3-2000 depending on the supplier. Gigabyte claims support for DDR2-1366+ on this board and we were able to hit DDR2-1300 with a less than impressive memory kit.
The P45 MCH is limited to 16 PCI-E lanes; unlike the P35, these lanes support the latest PCI Express 2.0 specification. PCI Express 2.0 doubles the standard bus bandwidth from 2.5 Gbit/s to 5 Gbit/s. We have not noticed any real performance differences between PCIe 1.0 and PCIe 2.0 in most cases, but as graphics technology improves, we expect to cross over that line shortly. Also keep in mind that two x8 PCI-E 2.0 slots are equivalent to two x16 PCI-E 1.x slots, provided you have PCI-E 2.0 cards installed.
The big news is that the P45’s PCI-E 2.0 slots can work in a dual x8 configuration for CrossFireX. The P35 had a slow x16/x4 CrossFire setup with the x4 slot running off the Southbridge. Compared to the dual x16 setup on the X38/X48 boards, we have not found any appreciable performance differences in GPU testing with AMD’s latest single GPU video cards.
With the P45 chipset comes the new ICH10R Southbridge. Except for official Turbo Memory support, consider this Southbridge to be a slightly revised ICH9R with support for six SATA II ports, AHCI, Matrix RAID, and twelve USB 2.0 ports.