Two years ago in Taiwan at Computex 2006 Gary Key and I stayed up all night benchmarking the Core 2 Extreme X6800, the first Core micro-architecture (Conroe core) CPU we had laid our hands on. While Intel retroactively applied its tick-tock model to previous CPU generations, it was the Core micro-architecture and the Core 2 Duo in particular that kicked it all off.

At the end of last year we saw the first update to Core, the first post-Conroe "tick" if you will: Penryn. Penryn proved to be a nice upgrade to Conroe, reducing power consumption even further and giving a slight boost to performance. What Penryn didn't do however was shake the world the way Conroe did upon its launch in 2006.

 

After every tick however, comes a tock. While Penryn was a die shrink of an existing architecture, Nehalem is a brand new architecture built on the same 45nm process as Penryn. It's sort of a big deal, being the first tock after the incredibly successful Core 2 launch.

 
731M transistors, four cores, eight threads

It's like clockwork with Intel; around six months before the release of a new processor, it's sent over to Intel's partners so they may begin developing motherboards for the chip. It was true with Northwood, Prescott, Conroe, Penryn and now Nehalem. And plus, did you really expect, on the eve of the two year anniversary of our first Core 2 preview, a trip to Taiwan for Computex without benchmarks of Nehalem? In the words of Balki Bartokomous, don't be ridiculous :)


Yep, that's what you think it is

Without Intel's approval, supervision, blessing or even desire - we went ahead and snagged us a Nehalem (actually, two) and spent some time with them.

(Sorry guys, stop making interesting chips and we'll stop trying to get an early look at them :)...)

Not One Nehalem, but Two
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  • SiliconDoc - Monday, July 28, 2008 - link

    lol- Buddy you are thinking. Reply
  • magreen - Thursday, June 05, 2008 - link

    Thanks for the amazing preview, Anand!

    I hope you and Gary will get us more Nehalem information quick like bunnies.
    Reply
  • yottabit - Thursday, June 05, 2008 - link

    Great Article Anand! I'm so excited for this new technology. But that socket and triple channel memory archetecture makes me want to puke in my mouth a little bit. It's very reminiscent to me of the Socket 423/RDRAM era. I have the feeling that they are going to release this setup for a lot of the early adopters and then screw them over by dropping the socket completely, when they decide that Dual Channel DDR3 is fast enough. I can't picture two platforms running side by side, with two entirely different sockets. People whant a Nehalem but need 4 gigs of ram will end up buying 6 Gigs of ram... and DDR3 ain't exactly cheap.

    I wish they had plans to through this into the mainstream faster. I'd love to have one of these, in dual channel variety. I'm still running an old early A64, and I'm holding out for these next gen processors in the next year or two.

    Its awesome to see that nice performance per clock increase, but the triple channel memory is a real slap in the face to me. Its like Intel saying "look, we increase clock for clock performance, but we also decided to use some brute force and raise our power consumption and motherboard complexity for no reason by adding another impractical memory channel". I don't see it as elegant at all. I think they are overcompensating for their lack of memory bandwith in recent times. :-

    Maybe AMD will have a chance to jump in with some nicer Phenom's before Nehalem comes out and actually capture some quad core market?
    Reply
  • npp - Thursday, June 05, 2008 - link

    I'm tired of all those people who just can live with the fact that the world is spinning and the CPUs that were reviewed here are simply far faster than the Penryn or Phenom you just bought yesterday... Get used to the fact, this is how thing happen today. Nehalem will be probably the most advanced x86 (x64) CPU when launched, and it just happened that Intel developed it - it could have been anybody else, say AMD, or nVidia, or whoever you prefer, no difference to me. Things go ahead, and some vendors simply get the job done first, in the grand scheme of things, it is all the same. All those fanboys I see around sound like some 3 year old children fighting for candy to me, It's amusing to see how AMD or Intel PR locked you up, guys.

    Now a brief question, aimed directly at Anand, I guess: I still can't figure out why memory performance is so low even via an advanced controller such as Nehalem's. As far as I can tell, 3-channel DDR3-1066 should be able to deliver up to 25,5 GB/s of bandwidth, far from the figures we see. How does this happen? And once more: you measured some 46ms latency altogether, how was that obtained? Assuming memory clock of 133Mhz, this should yield something like CAS4 (~30ms) latencies for the memory, am I right?
    Reply
  • fitten - Thursday, June 05, 2008 - link

    30us

    As far as single/dual/triple channel, it seems that Anand and gang were able to test with all three modes (you'll notice the comment about WinRAR being 10% faster with triple channel compared to single channel on the pre-release motherboard)... so you don't *have* to buy 3 sticks of memory... if you want 4GiB, you should be able to get 1x4 or 2x2 and leave the other slot(s) empty.
    Reply
  • npp - Thursday, June 05, 2008 - link

    It's all nanoseconds, of course, not milli- or micro, my fault. Never mind, I'm still awaiting some reasonable explanation about the "modest" bandwidth measured. 12GB/s copy is by no means little - I can't say if it's achievable via overclocking today, I'm not into that kind of business - but still I would guess no. Still, it seems little compared to the max. theoretical values. Reply
  • Anand Lal Shimpi - Thursday, June 05, 2008 - link

    I think we may have to wait for a final Nehalem platform before we can make any calls on memory bandwidth figures, but do keep in mind that the amount of usable memory bandwidth will depend largely on how it's being measured. If the algorithm is even slightly compute bound we won't see perfect scaling with theoretical memory bandwidth.

    I'm not sure how Everest measures bandwidth so I can't tell you exactly what numbers we should be seeing there, but it is useful for comparing a relative increase in bandwidth between Penryn and Nehalem.

    Take care,
    Anand
    Reply
  • npp - Thursday, June 05, 2008 - link

    Thank you very much, very kind of you to bother answering my question! Keep up the good work here at Anandtech. Reply
  • NINaudio - Thursday, June 05, 2008 - link

    I'm not sure hwy everyone is so concerned about DDR3 prices being high. A quick check shows that you can get a 2gig kit of ddr3-1600 for under $150 already. By the time Nehalem is out for mass consumption ddr3 will be even cheaper. I would say that it's pretty realistic to expect to be able to get a 3gig triple channel kit for under $100 and a 6gig triple channel kit for around $175 by the time nehalem is available to us. Reply
  • Anand Lal Shimpi - Thursday, June 05, 2008 - link

    What I'm really interested in is why Intel felt that Nehalem needed a three channel DDR3 memory controller. Will it really be necessary for higher clocked Nehalem (or is it Nehalems)? It'd be great for the versions of Nehalem with integrated graphics but I figured those would mostly be pushed into the mainstream, dual channel SKUs anyways. Looks like we'll have to wait at least a few more months before we can find out for sure.

    -A
    Reply

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