An Unbalanced L1 Cache: We Know Why

The Atom processor is outfitted with fairly large caches, which are quite necessary given its in-order architecture that's very sensitive to high memory latencies. We wrote the following in our initial Atom (Silverthorne) architecture discussion:

"The L1 cache is unusually asymmetric with a 32KB instruction and 24KB data cache, a decision made to optimize for performance, die size, and cost. The L2 cache is an 8-way 512KB design, very similar to what was used in the Core architecture.

While Silverthorne is built entirely on Intel's high-k/metal gate 45nm process, there is one major difference: SRAM cell size. Intel uses a 0.382 um^2 SRAM cell in Silverthorne compared to 0.346 um^2 in Core 2. Each SRAM cell is an 8 transistor design compared to 6 transistors in Core 2. The larger cell size increases the die size of Silverthorne but it draws less power and runs at a lower voltage."

At the time we didn't have a good explanation as to why the Atom's L1 cache wasn't made of equal sized instruction and data caches, which is usually how Intel designs its processors. Since then we have gotten some more insight into the design decision:

Historically, Intel would design a microprocessor for a particular manufacturing process (e.g. 65nm) and shoot for a target voltage, later attempting to lower that voltage when possible. Atom was designed around the absolute minimum voltage the manufacturing process (45nm) was capable of running at and the engineers were left with the task of figuring out what they could do, architecturally, given that requirement.

The perfect example of this approach to design is Atom's L1 instruction and data caches. Originally these two caches were small signal arrays (6 transistors per cell), they were very compact and delivered the performance Intel desired. However during the modeling of the chip Intel noticed that it was a limiter to being able to scale down the operating voltage of the chip.

Instead of bumping up the voltage and sticking with a small signal array, Intel switched to a register file (1 read/1 write port). The cache now had a larger cell size (8 transistors per cell) which increased the area and footprint of the L1 instruction and data caches. The Atom floorplan had issues accommodating the larger sizes so the data cache had to be cut down from 32KB to 24KB in favor of the power benefits. We wondered why Atom had an asymmetrical L1 data and instruction cache (24KB and 32KB respectively, instead of 32KB/32KB) and it turns out that the cause was voltage.

A small signal array design based on a 6T cell has a certain minimum operating voltage, in other words it can retain state until a certain Vmin. In the L2 cache, Intel was able to use a 6T signal array design since it had inline ECC. There were other design decisions at work that prevented Intel from equipping the L1 cache with inline ECC, so the architects needed to go to a larger cell size in order to keep the operating voltage low.

The end result of this sort of a design approach is that the Atom processor is able to operate at its highest performance state (C0) at its minimum operating voltage.

Hardware Prefetchers: So Necessary

Atom features two hardware prefetchers, one that prefetches from the L2 cache into the L1 data cache and one from memory into the L2 cache.

Hardware prefetching is unbelievably important when dealing with an in-order core because as we've mentioned time and time again, not having data available in cache means that the pipelines will stall until that data is available.

The obvious long term solution to the problem of data starvation is to integrate the memory controller on die. With no 45nm MCH design ready by the time the Atom design was complete, Intel has to wait until the second generation Atom (codename: Moorestown) to gain an on-die memory controller.

Fighting Power Consumption...with a Longer Pipeline? Building by FUBs
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  • FlakeCannon - Wednesday, April 02, 2008 - link

    This was an absolutely fantastic article as far as I'm concerned. One of the best I've read from AnandTech. I'm truly impressed with the amount of effort and dedication that the engineers at Intel put into the Atom. Thought the consumer may not see its importance today the Atom will continue to develop one throughout the next 2 years and show why this is such a huge step in the right direction. I really think that this article outlines very well the architecture involved and where it intends to lead Intel and others in the future.

    I'm always impressed to see Intel take architecture that was revolutionary in its time 15 years ago in the Pentium and Pentium Pro and resurrect it in modern day fashion with help of the Dothan Pentium M architecture and even things borrowed from the miserable Netburst technology that 15 years later I believe will once again create a product revolutionary in nature. I was never able to appreciate it in the days of the Pentium but certainly can now.

    This is one product I think is deserving of being excited about.
    Reply
  • fitten - Wednesday, April 02, 2008 - link

    What does an on-die memory controller have to do with ILP? Reply
  • Anand Lal Shimpi - Wednesday, April 02, 2008 - link

    Woops, I've clarified the statement :)

    Take care,
    Anand
    Reply
  • erwos - Wednesday, April 02, 2008 - link

    I was thinking that this would be a fantastic platform for making a small, silent HTPC box for doing streaming media, but the lack of 1080p output kills that to a large extent. I know it's not a big priority for the first revision given the UMPC targeting, but I hope the "Atom 2" does try to squeeze that feature in. Reply
  • FITCamaro - Wednesday, April 02, 2008 - link

    It could always be paired with a different, more capable graphics core. Reply
  • ltcommanderdata - Wednesday, April 02, 2008 - link

    It;d be very interesting to see how the 1.86GHz Silverthorne stacks up against a 1.8GHz P4 Northwood, a 1.86GHz Dothan, a 1.8GHz Conroe-L based Celeron, and a 1.8GHz Athlon 64.

    I wonder if Apple is going to refresh AppleTV with Silverthorne since it seems ideal with replace the current 1GHz ULV Dothan in there.
    Reply
  • yyrkoon - Wednesday, April 02, 2008 - link

    Well at least Intel did not name their Atom CPUs the 'Atom Z80' . . . heh.

    Anyways, this is good for our future, as the mITX, and pITX 'systems' now days are still kind of large-ish, and cost quite a bit of money for what they are. Though, I think that putting a web browser on just any old appliance in the house would be way overkill, and possibly a very serious mistake. A TV with a web browser ? An Oven ? Please . . . this is why we have PCs, and micro mobile devices.

    Recently a friend and myself have been working on an embedded project, and I can see the potential here, but a 'problem' does exist. Some of the things you would want to do with such a processor . . . well lets just say there still would not be enough processing power. That being said, I do not see why these could not help make a TVs/HD-DVD player menu operate faster.


    Reply
  • pugster - Thursday, April 03, 2008 - link

    It certainly sounds nice, but the atom processor cost alot because some of the higher end models cost more than $100 each. I find it surprising that their Polosbo chipset is manufactured at 130mm. It probably came from one of their foundries that was due to upgrade to 32mm sometime next year anyways. They could've earily manufactured at 65mm.

    Somehow I don't see their product as mature and maybe the next gen product they would have a cpu and the north/south bridge in the same die.
    Reply
  • lopri - Wednesday, April 02, 2008 - link

    I honestly don't get the excitement. Should I? I mean, I wouldn't feel comfortable with one gigantic company controlling every single electronics in our life. If Intel opens up the X86 and everyone can compete on even end, then maybe. Since that won't happen, the future looks scary enough. Reply
  • clnee55 - Wednesday, April 02, 2008 - link

    NO, how can you get excitement. I am already bored with your conspiracy theory. Let's talk about tecnical issue here. Reply

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